TTL Compatible... NOT! ( WDC )

[enso]

Dr Jefyll wrote:

...There's a whole other world out there, where 5V supplies are not the norm. (Martin A, you hinted at this, too.)...

I feel like I'm not in on some private joke! What is that world, where 5V is not the norm? An who are these TTL-hating mysterious customers of WDC? Did I miss some solar-road deal with Elon Musk?

[BigDumbDinosaur]

drogon wrote:

There is no buffer on the '816 data bus just a latch on the data bus to provide A16:23 (Implemented in a GAL).

Adding to the merriment, the GAL's outputs are TTL-compatible.

[BigDumbDinosaur]

enso wrote:

Now that I think about it, Apples and Commodores have buffered busses.

They have them because of the weak fanout of individual 74LS gates and the NMOS 6502. The buffers' outputs are also TTL, so all that is gained is increased drive current.

[GARTHWILSON]

enso wrote:

Dr Jefyll wrote:

...Pullup resistors are tiny and cheap...

I imagine resistors would slow down the transitions. Is there enough slack to accommodate the delay? I have no idea what the capacitance of the bus lines is...

Resistors would slow it down if they were in series between the driving end and the receiving end. They will not slow it down though when they're just giving a little help to pull up, being connected from the signal line to VDD.

Ingenious test method, Jeff!

[BigDumbDinosaur]

Dr Jefyll wrote:

Pullup resistors are tiny and cheap.

However, they are definitely not an ideal solution, since some amount of parasitic capacitance is always there to round off edges for you. If one is going to go that route they need to, as Garth noted, place the pullups as physically close to the TTL-compatible voltage source as is possible...which creates a conundrum. There is almost always more than one such source. Which source is the one next to which the pullups should be placed?

Quote:

And, as Garth noted, an '816 will usually have a '245 nearby anyway. Just be sure you specify a "T" variant, such as 'HCT245 or 'AHCT245.

I would not use HCT logic for this application. As any transceiver inserts prop delay into the data bus, it makes sense to utilize a very fast logic family to maintain timing headroom. My choice would be a 74AHCT245 or 74VHCT245 on a system with only RAM, ROM and a single I/O device. Otherwise, I'd go with a 74ACT245 to handle greater bus loading.

[BillO]

Dr Jefyll wrote:

TTL Compatible... NOT! ( modern WDC CPU's )

In this thread I'd like to talk about the advisability of mixing modern WDC CPU's with RAM's, ROM's or PLD's etc whose output specifications only guarantee TTL voltage levels.

I honestly don't think it's much of an issue. I know I will more than likely, for the sake of future visits to this topic, be ignored and the argument will entertain us forever. So be it.

Bold assertion warning: If the devices (ROM, RAM PLD) are CMOS, you will have no issue whatsoever.

You have to consider a few things:

1) Spec Sheets are created for 2 reasons. A) (the lesser reason) To give engineering guidance for reliable design purposes. B) (by far the main reason) To prevent companies like TI from being raked through the legal coals when a cruise missile misses the bunker in Syria and hits the White House instead because one of their 54LS32's did not meet spec. Or something to that effect.

2) Many of the devices in question were released into a market where TTL compatibility was still paramount. As deployment environments changed these devices were taken off the market so there was never a need to update their specs. As an example. Those TTL voltage specs were given for TTL loads. You will see them all quoted of a 400 uA load. In modern CMOS environments a load of 50 uA would be considered high.

3) Back in 80's when I was a bench tech at a teleprinter manufacturing plant I had to do my hours in QA like all of us. More than 99.9% of the TTL devices met or exceeded their "typical" output rating under full load. ~3.4V So the great preponderance of these ancient TTL devices should work just fine.

4) Basically 100% of CMOS devices have the nice, simple stacked MOSFET outputs we are all familiar with. They all work the same. In fact, those guaranteed to work with TTL loads should be expected to be more robust than to those not guaranteed to work with TTL loads.

As a exhibit I have attached the datasheet for the ST Micro M27C1001. Look at the output specifications on page 13. They list guaranteed output voltages for TTL (400 uA) and CMOS (100 uA). These same specifications can be expected (dare I say relied on) for any CMOS device that is TTL capable. This is why, when we use these CMOS RAMs, ROMs and PLDs with CMOS CPUs, they work to rated speeds and beyond.

So, if you're a hobbyist building your next interesting gadget then go for it. If you get the 1 in 10000++ device that does not pass muster, then gleefully thumb-toss it into the trash and put another in it's place (if this indeed happens in your life span) and carry on.

However, if you work for HP (who are they now?) building the next gen heart-lung machine or for General Dynamics building the next stealth AI bomb, you might want to take other precautions.

[enso]

BillO wrote:

...I honestly don't think it's much of an issue....

Yeah, except that if ignored, your design may not work. It probably will, but not necessarily.

Keep in mind that not only are WDC chips not TTL compatible, they are not even CMOS compatible - at least not with any 5V SRAM or EEPROM or FLASH that I've looked at. All the devices I've looked at specify minimum High voltage as 2.4V! Some parts even lower.

Combined with other foolishness (marginal construction techniques, 2-layer PCB layout, inadequate decoupling, or everything Ben Eater teaches), it makes it more likely the design will fail. So it is very important to keep it in mind.

BigDumbDinosaur wrote:

Adding to the merriment, the GAL's outputs are TTL-compatible.

Good catch, BDD.

[enso]

Curious.

While I was lamenting that WDC chips are technically not compatible with all non-WDC devices, it gets better:

WDC CPUs are not compatible with WDC peripherals!

The W65C22S specs show minimum Vih voltages as 2.0V, and Voh as 2.4V.

The W65C22N numbers are even weirder: Vih is VDD * 0.8, and Voh is cleverly omitted.

I am pissing my pants on the floor laughing. And rolling.

I think WDC CPUs are not technically compatible with any other devices. I am pretty sure they are not compatible with themselves, as specified. That's amazing.

[plasmo]

I agree with Billo that Voh spec is exceedingly conservative. If you still have TI's TTL databook, look into the first section where it talked about typical characteristic of TTL logic family. I attach characteristic of LS family and look at figure D5. 74LS has no problem getting to 3.0V with 15mA output.

I'm a big user of Altera CPLD. Their data sheet also says 2.4V minimum Voh, but buried in the datasheet is this output drive characteristic. It can drive to 3.0V with 30mA output.
Bill

[GARTHWILSON]

enso wrote:

WDC CPUs are not compatible with WDC peripherals!

The W65C22S specs show minimum Vih voltages as 2.0V, and Voh as 2.4V.

That would definitely be messed up. According to my own tests though, the W65C22 can even pull up to within 0.8V of the positive rail at 19mA.

[enso]

I think that the take-away here is that the specifications are bungled, and cannot be relied upon. It would be nice to have a safety-net of 'do this and we guarantee it will work'; instead we have 'it seems to be better than the spec, so we can hope it will work'. We have a bunch of unspecified silicon and we are left to empirically figuring out our safety margins.

In the end it does not matter that much. We will work around this like we work around all other WDC blunders. It's another embarrassing low point for WDC. Not that they give a hoot about us.

[BigDumbDinosaur]

enso wrote:

WDC CPUs are not compatible with WDC peripherals!

The W65C22S specs show minimum Vih voltages as 2.0V, and Voh as 2.4V.

The W65C22N numbers are even weirder: Vih is VDD * 0.8, and Voh is cleverly omitted.

Try not to soil your skivvies too much over this. Over the years, WDC data sheets have had numerous, often egregious, errors. I've not used the W65C22S in anything but know from Garth's writings that that device can drive its outputs quite hard. I strongly suspect that VOH rating is a typo.

As for the inputs, if it indeed can recognize 2 volts as a logic 1 then that's a good thing. That means it will reliably operate as a replacement for an NMOS 6522 in a VIC-20.

[BigDumbDinosaur]

GARTHWILSON wrote:

enso wrote:

WDC CPUs are not compatible with WDC peripherals!

The W65C22S specs show minimum Vih voltages as 2.0V, and Voh as 2.4V.

That would definitely be messed up. According to my own tests though, the W65C22 can even pull up to within 0.8V of the positive rail at 19mA.

As I said, WDC data sheets have been rife with errors over the years. Documentation has definitely not been their strong suit.

19mA is a lot of output and achieving a VOH of 4.2 with that kind of load says the C22S is quite robust.

[BigDumbDinosaur]

BillO wrote:

As a exhibit I have attached the datasheet for the ST Micro M27C1001.

'Tis a shame the 27C1001 has become unobtanium. Even my stalwart EPROM, the AMD 27C256-55 has gone the way of $1.00-a-gallon gas.

[BigDumbDinosaur]

BigDumbDinosaur wrote:

Dr Jefyll wrote:

BigDumbDinosaur wrote:

I'd find it hard to believe [...]

Do you believe that I measured the data bus input transition voltage for three 65xx CPUs? I did.

When I applied 2.4V -- a valid TTL high -- to the WDC chips, they thought it was a zero. To perceive a one, the '816 needed 2.57 volts and the 'C02 needed 2.6.

If that is the case, it suggests the MPUs' inputs are Schmitt-triggered, as the actual CMOS "no man's land" is several volts wide. Without Schmitt triggering, I would not expect to see a transition at VDD ÷ 2 as you are reporting.

Assuming my supposition is correct (I may soon know—I have a query into WDC on this), it would explain why the C02/816 will work despite being driven by a device with TTL-compatible outputs.

I queried WDC on this and received a reply from Bill Mensch. It is short and to the point:

• Generally speaking the inputs are not Schmitt-triggered. That said, NMI is Schmitt-triggered since it is edge-triggered.
  
  I think that the reason most if not all systems that use the W65C02S, W65C21S, W65C22S and W65C816S work in legacy systems is because I designed my chips to be rather forgiving in many ways. The minimum “1” level of a TTL interface is most likely around 3-3.5V which would be enough for the “S” chips to recognize a “1”. The “0” level is no problem.

Earlier, in another message, Bill had said:

• The inputs for the W65C816S is [sic] set for 50% of VDD. That said, if VDD is 5.0V then the 1-0 and 0-1 transition happens at approximately 2.5V. At VDD 3.3V the 1-0 and 0-1 will occur around 1.65V.
  
  The outputs drive the 1 to VDD and the 0 to VSS and can probably drive about 5 or move TTL loads.

The above information explains what Jeff was seeing with his test rig. What I find especially interesting is what is implied by the highlighted text: the transition between one logic state and the other is sharply-defined and not particularly CMOS-like, which it seems would greatly improve the MPU's ability to distinguish a valid logic 1 at its inputs.

So I think the takeaway is we probably have nothing about which to be concerned in interfacing the WDC MPU's to devices that produce TTL outputs, provided the design isn't excessively loading the outputs. If you are at all concerned about it, stick a 74AHCT/VHCT/ACT245 transceiver in there to act as a level converter. Just be aware of the prop delay and its possible effects on your timing.

Oh yes! Almost forgot! It looks as though I will be taking Jeff out drinking the next time I'm in Stratford or the next time he comes to the Chicago area.