6502.org

Without having read the full thread, but on the C64 you cannot latch the address lines on the clock positive edge. The C64 clock cycle is divided into the low phase, where the VIC owns the bus, and the high phase where the CPU owns the bus. Latching at the positive edge of the clock, you will most likely rather use the VIC address, or some mixup between CPU and VIC addresses.

André

Edit: Pls ignore this post. The C64 reference mentally spilled over from the previous topic I was reading... I should probably just go to bed...

BigEd recommends unidirectional streams. In this case, make video display write only. Indeed, a write only display also improves security.

BigDumbDinosaur recommends a qualified write strobe. In this case, make address and data latches level triggered when clock HIGH, R/W LOW and negative logic address strobe LOW.

In the other clock domain, video RAM may continuously alternate between read and write. Reads are sent to screen. Writes are from the level triggered latches. This arrangement continuously hammers RAM with needless writes. Regardless, the intention is to continuously write stable data where the maximum frequency of writes from processor to latch is less than half of the frequency of writes from latch to RAM. Consider it as a one word deep, clock domain crossing, FIFO which never empties.

Ah, you may say, cases exist where random data may be scribbled to random locations! Well, we have the luxury of operating any number of cycles behind the processor. Therefore, in the video clock domain, we may have a conveyer of two or more sets of edge triggered latch. If contents differ then direct writes to the last byte of the video buffer or otherwise modulate writes.

If it looks wrong then you are doing it correctly. plasmo, responding to jds, notes "The complexity of WRITING to video memory will rapidly overwhelm the simple VGA displaying logic."

Apparently, I downloaded a legal PDF of the book Advanced FPGA Design by Steve Kilts from Wiley in Feb 2012. In Oct 2021, I actually bothered to read it. (I also downloaded your circuit CAD files in Jan 2021 and looked at them in Aug 2021 after I had learned enough about KiCAD to be helpful to your project.)

In my message from Sun 16 May 2021, I suggested having one critical bit of signal and delaying the data path by two or three clock cycles. I probably gleaned this from reading the forum archive in full which contains relevant information about FPGA design and UART FIFO. A "double flop" is the established technique to handle clock domain crossing. A third flip-flop is a luxury which adds reliability in the edge case when a CMOS input has not settled. The third flip-flop is often skipped when latency is critical or resources are tight. For your case, always include the third flip-flop.