Re: Theorizing about interfacing a NMOS VIC-II with a 65cxx
Posted: Thu Jun 03, 2021 10:34 am
brain wrote:
Beamracer implements a dual port functionality in the CPLD/FPGA, just like I described initially.
I am wondering what you meant with the above? BeamRacer block diagram shows what is implemented and I am not sure how to match it with what you wrote.
