Re: Using W65C265S in hobbyist projects?
Posted: Sat Jun 30, 2018 6:03 pm
From the W65C265S (Sept 13, 2010) datasheet:
2.2 RUN and SYNC outputs with WAI and STP defined (RUN)
2.2.1 The RUN function of the RUN output is pulled low as the result of a WAI or STP instruction. RUN is
used to signal an external oscillator to start PHI2. The processor is stopped when RUN is low.
2.2.2 When BCR3=1 (emulation mode), the SYNC function (SYNC=1 indicates an opcode fetch) is
multiplexed on RUN during PHI2 low time and RUN is multiplexed during PHI2 high time. When
BCR3=0 (normal operating mode), the RUN function is output during the entire clock cycle. An ICE
system can demultiplex RUN to provide full emulation capability for the RUN function.
2.2.3 The BE input has no effect on RUN.
2.2.4 When RUN goes low the PHI2 signal may be stopped when high or low; however, it is recommended
PHI2 stop in the high state. When RUN goes high due to an enabled interrupt or reset, the
internal PHI2 clock is requested to start. The clock control function is referred to as the RUN function
of RUN.
2.2.5 The WAI instruction pulls RUN low during PHI2 high time. RUN stays low until an enabled interrupt is
requested or until RESB goes from low to high, starting the microprocessor.
2.2.6 The STP instruction pulls RUN low during PHI2 high time and stops the internal PHI2 clock.
RUN remains low and the clock remains stopped until RESB goes from low to high.
2.2.7 FCLK can be started or stopped by writing to System Speed Control Register (SSCR) bit 0. When
SSCR0=0 (reset forces SSCR0=0), FCLK is stopped. When SSCR0=1, FCLK is started. When
starting FCLK oscillator, the system software should wait (100 milliseconds or an appropriate amount
of time) for the oscillator to be stable before using FCLK.
2.2 RUN and SYNC outputs with WAI and STP defined (RUN)
2.2.1 The RUN function of the RUN output is pulled low as the result of a WAI or STP instruction. RUN is
used to signal an external oscillator to start PHI2. The processor is stopped when RUN is low.
2.2.2 When BCR3=1 (emulation mode), the SYNC function (SYNC=1 indicates an opcode fetch) is
multiplexed on RUN during PHI2 low time and RUN is multiplexed during PHI2 high time. When
BCR3=0 (normal operating mode), the RUN function is output during the entire clock cycle. An ICE
system can demultiplex RUN to provide full emulation capability for the RUN function.
2.2.3 The BE input has no effect on RUN.
2.2.4 When RUN goes low the PHI2 signal may be stopped when high or low; however, it is recommended
PHI2 stop in the high state. When RUN goes high due to an enabled interrupt or reset, the
internal PHI2 clock is requested to start. The clock control function is referred to as the RUN function
of RUN.
2.2.5 The WAI instruction pulls RUN low during PHI2 high time. RUN stays low until an enabled interrupt is
requested or until RESB goes from low to high, starting the microprocessor.
2.2.6 The STP instruction pulls RUN low during PHI2 high time and stops the internal PHI2 clock.
RUN remains low and the clock remains stopped until RESB goes from low to high.
2.2.7 FCLK can be started or stopped by writing to System Speed Control Register (SSCR) bit 0. When
SSCR0=0 (reset forces SSCR0=0), FCLK is stopped. When SSCR0=1, FCLK is started. When
starting FCLK oscillator, the system software should wait (100 milliseconds or an appropriate amount
of time) for the oscillator to be stable before using FCLK.
