Re: Wiring SRAM to W65C265SQXB
Posted: Thu Apr 26, 2018 8:45 pm
/RESET wrote:
Ok, we are fooling the address logic of the chip ... when trying to access 00:E000 the chip thinks is its internal ROM area and thus it doesn't drive the external address or data bus and handles everything internally. But when we access 01:E000 the chip thinks we access the RAM above 64K and drives the external address and data bus letting us read/write the area which otherwise would be hidden to us.
Since we only use 16 address lines, any address above 00:FFFF will roll over to the lower 64K, what means it doesn't matter if we would use 01:Exxx, 04:Exxx or 08:Exxx any bank except 00 will have the same effect, right?
Since we only use 16 address lines, any address above 00:FFFF will roll over to the lower 64K, what means it doesn't matter if we would use 01:Exxx, 04:Exxx or 08:Exxx any bank except 00 will have the same effect, right?
We're not "fooling" anyone. Rather, we're simply "under specifying". The internal chip select logic within the MCU is quite specific, whereas, we're just a bit more ham fisted. So, your 64K is essentially mapped to "everyplace the MCU DOESN'T map to".
You can see that if you wanted to map your 64K to bank 1, we'd need to check that A16-A23 equals "00000001", and you can imaging the gates and circuitry necessary to discern that. That's one aspect of what makes the CS logic on the chip so nice. They reduced a whole bunch of decode logic to just a few pins for us to use. Combined with the automatic decoding of the A16-A23 (which are normally multiplexed with the Data Bus), and you can see how the MCU simplifies a bunch of the support circuitry needed for an '816.