Timing Error with Kowalski Simulator

[BigDumbDinosaur]

8BIT wrote:

Druzyek wrote:

Would it make sense to make a list of bugs we might be able to fix?

Sure, but lets wait to see if we can get a more recent source to start with. Some bugs may have been fixed, such as BDD's conditional assembly.

I'm hoping we can get the 1.2.12 source.

Daryl

I haven't received a reply but also the message I sent didn't bounce. We'll see...

[BitWise]

Daryl, where did you find the missing afx files needed to make it compile?

[8BIT]

Well,

I ran the Visual6502 this morning using this code:

Code: Select all

	*=	$0000

	LDX	#$80
	LDY	#$81
LOOP	LDA	#$21
	ADC	$0080, X
	ADC	$0080, Y
	ADC	($80), Y
	SED
	JMP	LOOP

0080	.WORD	$0082

0100	.BYTE	$22
0101	.BYTE	$23
0102	.BYTE	$24

The first time through, the ADC instructions used the extra cycle for page crossing, as expected. After the SED and jump, they used the exact same cycles. I thought that if decimal mode was set, these will use an added cycle for any BCD adjust. I even tried it with a carry past 99 but the extra cycle does not appear.

I adjusted X & Y so a page was not crossed and I used 1 less cycle as expected. The BCD math did not add a cycle in this case either.

Am I missing something, or is this a Visual6502 bug?

Here's the trace:

Code: Select all

cycle	ab	db	rw	Fetch	pc	a	x	y	s	p
0	0000	a2	1	LDX #	0000	aa	00	00	fd	nv‑BdIZc
0	0000	a2	1	LDX #	0000	aa	00	00	fd	nv‑BdIZc
1	0001	80	1			0001	aa	00	00	fd	nv‑BdIZc
1	0001	80	1			0001	aa	00	00	fd	nv‑BdIZc
2	0002	a0	1	LDY #	0002	aa	80	00	fd	Nv‑BdIzc
2	0002	a0	1	LDY #	0002	aa	80	00	fd	Nv‑BdIzc
3	0003	81	1			0003	aa	80	00	fd	Nv‑BdIzc
3	0003	81	1			0003	aa	80	00	fd	Nv‑BdIzc
4	0004	a9	1	LDA #	0004	aa	80	81	fd	Nv‑BdIzc
4	0004	a9	1	LDA #	0004	aa	80	81	fd	Nv‑BdIzc
5	0005	21	1			0005	aa	80	81	fd	Nv‑BdIzc
5	0005	21	1			0005	aa	80	81	fd	Nv‑BdIzc
6	0006	7d	1	ADC Abs,X	0006	21	80	81	fd	nv‑BdIzc
6	0006	7d	1	ADC Abs,X	0006	21	80	81	fd	nv‑BdIzc
7	0007	80	1			0007	21	80	81	fd	nv‑BdIzc
7	0007	80	1			0007	21	80	81	fd	nv‑BdIzc
8	0008	00	1			0008	21	80	81	fd	nv‑BdIzc
8	0008	00	1			0008	21	80	81	fd	nv‑BdIzc
9	0000	a2	1			0009	21	80	81	fd	nv‑BdIzc
9	0000	a2	1			0009	21	80	81	fd	nv‑BdIzc
10	0100	22	1			0009	21	80	81	fd	nv‑BdIzc
10	0100	22	1			0009	21	80	81	fd	nv‑BdIzc
11	0009	79	1	ADC Abs,Y	0009	21	80	81	fd	nv‑BdIzc
11	0009	79	1	ADC Abs,Y	0009	21	80	81	fd	nv‑BdIzc
12	000a	80	1			000a	43	80	81	fd	nv‑BdIzc
12	000a	80	1			000a	43	80	81	fd	nv‑BdIzc
13	000b	00	1			000b	43	80	81	fd	nv‑BdIzc
13	000b	00	1			000b	43	80	81	fd	nv‑BdIzc
14	0001	80	1			000c	43	80	81	fd	nv‑BdIzc
14	0001	80	1			000c	43	80	81	fd	nv‑BdIzc
15	0101	23	1			000c	43	80	81	fd	nv‑BdIzc
15	0101	23	1			000c	43	80	81	fd	nv‑BdIzc
16	000c	71	1	ADC (zp),Y	000c	43	80	81	fd	nv‑BdIzc
16	000c	71	1	ADC (zp),Y	000c	43	80	81	fd	nv‑BdIzc
17	000d	20	1			000d	66	80	81	fd	nv‑BdIzc
17	000d	20	1			000d	66	80	81	fd	nv‑BdIzc
18	0020	81	1			000e	66	80	81	fd	nv‑BdIzc
18	0020	81	1			000e	66	80	81	fd	nv‑BdIzc
19	0021	00	1			000e	66	80	81	fd	nv‑BdIzc
19	0021	00	1			000e	66	80	81	fd	nv‑BdIzc
20	0002	a0	1			000e	66	80	81	fd	nv‑BdIzc
20	0002	a0	1			000e	66	80	81	fd	nv‑BdIzc
21	0102	24	1			000e	66	80	81	fd	nv‑BdIzc
21	0102	24	1			000e	66	80	81	fd	nv‑BdIzc
22	000e	f8	1	SED		000e	66	80	81	fd	nv‑BdIzc
22	000e	f8	1	SED		000e	66	80	81	fd	nv‑BdIzc
23	000f	4c	1			000f	8a	80	81	fd	NV‑BdIzc
23	000f	4c	1			000f	8a	80	81	fd	NV‑BdIzc
24	000f	4c	1	JMP Abs	000f	8a	80	81	fd	NV‑BDIzc
24	000f	4c	1	JMP Abs	000f	8a	80	81	fd	NV‑BDIzc
25	0010	04	1			0010	8a	80	81	fd	NV‑BDIzc
25	0010	04	1			0010	8a	80	81	fd	NV‑BDIzc
26	0011	00	1			0011	8a	80	81	fd	NV‑BDIzc
26	0011	00	1			0011	8a	80	81	fd	NV‑BDIzc
27	0004	a9	1	LDA #	0004	8a	80	81	fd	NV‑BDIzc
27	0004	a9	1	LDA #	0004	8a	80	81	fd	NV‑BDIzc
28	0005	21	1			0005	8a	80	81	fd	NV‑BDIzc
28	0005	21	1			0005	8a	80	81	fd	NV‑BDIzc
29	0006	7d	1	ADC Abs,X	0006	21	80	81	fd	nV‑BDIzc
29	0006	7d	1	ADC Abs,X	0006	21	80	81	fd	nV‑BDIzc
30	0007	80	1			0007	21	80	81	fd	nV‑BDIzc
30	0007	80	1			0007	21	80	81	fd	nV‑BDIzc
31	0008	00	1			0008	21	80	81	fd	nV‑BDIzc
31	0008	00	1			0008	21	80	81	fd	nV‑BDIzc
32	0000	a2	1			0009	21	80	81	fd	nV‑BDIzc
32	0000	a2	1			0009	21	80	81	fd	nV‑BDIzc
33	0100	22	1			0009	21	80	81	fd	nV‑BDIzc
33	0100	22	1			0009	21	80	81	fd	nV‑BDIzc
34	0009	79	1	ADC Abs,Y	0009	21	80	81	fd	nV‑BDIzc
34	0009	79	1	ADC Abs,Y	0009	21	80	81	fd	nV‑BDIzc
35	000a	80	1			000a	43	80	81	fd	nv‑BDIzc
35	000a	80	1			000a	43	80	81	fd	nv‑BDIzc
36	000b	00	1			000b	43	80	81	fd	nv‑BDIzc
36	000b	00	1			000b	43	80	81	fd	nv‑BDIzc
37	0001	80	1			000c	43	80	81	fd	nv‑BDIzc
37	0001	80	1			000c	43	80	81	fd	nv‑BDIzc
38	0101	23	1			000c	43	80	81	fd	nv‑BDIzc
38	0101	23	1			000c	43	80	81	fd	nv‑BDIzc
39	000c	71	1	ADC (zp),Y	000c	43	80	81	fd	nv‑BDIzc
39	000c	71	1	ADC (zp),Y	000c	43	80	81	fd	nv‑BDIzc
40	000d	20	1			000d	66	80	81	fd	nv‑BDIzc
40	000d	20	1			000d	66	80	81	fd	nv‑BDIzc
41	0020	81	1			000e	66	80	81	fd	nv‑BDIzc
41	0020	81	1			000e	66	80	81	fd	nv‑BDIzc
42	0021	00	1			000e	66	80	81	fd	nv‑BDIzc
42	0021	00	1			000e	66	80	81	fd	nv‑BDIzc
43	0002	a0	1			000e	66	80	81	fd	nv‑BDIzc
43	0002	a0	1			000e	66	80	81	fd	nv‑BDIzc
44	0102	24	1			000e	66	80	81	fd	nv‑BDIzc
44	0102	24	1			000e	66	80	81	fd	nv‑BDIzc
45	000e	f8	1	SED		000e	66	80	81	fd	nv‑BDIzc
45	000e	f8	1	SED		000e	66	80	81	fd	nv‑BDIzc
46	000f	4c	1			000f	90	80	81	fd	NV‑BDIzc
46	000f	4c	1			000f	90	80	81	fd	NV‑BDIzc

Daryl

[8BIT]

BitWise wrote:

Daryl, where did you find the missing afx files needed to make it compile?

Well, that was a huge experiment. I downloaded the MS Visual Studio Express 2008 from MS. I found out that does not include support for Microsoft Foundation Class libraries. (You need the standard or higher version for that - and lots of $$$) There were several web sites saying to install the MS 2008 Driver Design Kit as it has the MFC libraries. It also mentioned its an older version of the MCF's AND you cannot link statically or use debug mode, you can only link dynamically (which means you have to include the separate run time files). I actually tried this and got it to compile, but the 6502.exe would crash about 50% of the time.

I tried to static link it and but it was missing the nafxcw.lib file. I did a few searches for that file and found it in a dotnet installation archive. I dug a little deeper and found the whole MFC/ATL library in that archive. So, I downloaded the archive and placed the ATLMFC folder in my VC++ folder and added it to the LIB and INC paths.

That allowed me to do a static compile. I had a few configuration changed to tweak in the Release mode, but I eventually got it to compile without errors.

Hope this helps.

Daryl

[BigEd]

I think only the 65C02 takes an extra cycle for BCD. It was one of the innovations of the 6502 - the sole patent I think - that it takes no extra cycles for BCD.

[8BIT]

Ok, thanks! The Kowalski simulator is adding 1 cycle for both 6502 and 65C02. More artifacts to document.

Daryl

[BigDumbDinosaur]

8BIT wrote:

Ok, thanks! The Kowalski simulator is adding 1 cycle for both 6502 and 65C02. More artifacts to document.

Daryl

Are you placing the following statement at the beginning of your source file?

Code: Select all

	.opt proc65c02

This statement should be the first line in the main source file and should not be repeated in INCLUDE files. It identifies the target processor. I don't know which MPU is the default absent this statement.

The form of the above statement I use is:

Code: Select all

	.opt proc65c02,caseinsensitive

The caseinsensitive part tells the assembler to ignore case in all non-quoted strings, which is "traditional" behavior for 6502 assemblers.

[8BIT]

I am setting the processor type in the menu: Simulator->Options->General

I just found these pages in the Tutorials section of this website.
http://www.6502.org/tutorials/6502opcodes.html
http://www.6502.org/tutorials/65c02opcodes.html

They seem to be the best single source that I have found so far. I will use these as a baseline for documenting behavior and then work on the Simulator modifications.

Two notes from the 65C02 tutorial:
JMP (abs, x) appears to add 1 cycle for a page crossing but is not noted
BBR and BBS will add 1 cycle if a page boundary is crossed but is not noted.

Daryl

[BigDumbDinosaur]

Just discovered another bug in the simulator having to do with macro processing. I accidentally passed one too many parameters with a macro call—the macro only accepts one parameter—and the assembler got hung up in an error loop when it tried to assemble the statement. I had to go into the task manager and manually kill the simulator to break the loop. Fortunately, I had saved the source file before this happened.

[8BIT]

BigDumbDinosaur wrote:

Are you placing the following statement at the beginning of your source file?

Code: Select all

	.opt proc65c02,caseinsensitive

The caseinsensitive part tells the assembler to ignore case in all non-quoted strings, which is "traditional" behavior for 6502 assemblers.

I just discovered that setting the .opt proc65c02 (or .opt proc6502) statement will allow the assembler to build the proper code, but the Simulator will use the mode set in the Simulator->Options->General menu. In other words, you can have the Simulator set for 6502 and the .opt proc65c02 will build a source that uses 65C02 instructions and when you run the simulator, it works in 6502 mode and treats the 65C02 code as invalid instructions.

If you set the Simulator flag to 65C02 (Simulator->Options->General), it will also assemble using the 65C02 opcode set unless you add the .opt proc6502 statement to force NMOS opcodes.

I have almost finished the modifications to the 1.2.6 source to fix the cycle counting. I will work on verifying the behavior for both 6502 and 65C02 modes.

I am still hoping we can get a more current source to build from.

Daryl

[BigDumbDinosaur]

8BIT wrote:

I am still hoping we can get a more current source to build from.

No response as yet from Mike Kowalski. I contacted him on Tuesday the 14th, so I'll wait a little longer before trying again.

[8BIT]

Thanks! There's no real hurry from my perspective.

Daryl

[8BIT]

I've updated the V1.2.6 source to correct the cycle counting for both the 6502 and 65C02, based on as many sources as I could find. I also fixed the Command Log so it would show the disassembled line and resulting registers on the same line. Before, the resulting registers were 1 line below the source. I also added the number of computed cycles for each instruction as well.

It went from this:

Code: Select all

1000  A9 90     LDA #$90       A:00 X:00 Y:00 F:20 S:1ff 
1002  85 90     STA $90        A:90 X:00 Y:00 F:a0 S:1ff 
1004  A9 02     LDA #$02       A:90 X:00 Y:00 F:a0 S:1ff 
1006  85 91     STA $91        A:02 X:00 Y:00 F:20 S:1ff 

to this:

Code: Select all

1000  A9 90     LDA #$90       A:90 X:00 Y:00 F:a0 S:1ff Cycles=2
1002  85 90     STA $90        A:90 X:00 Y:00 F:a0 S:1ff Cycles=3
1004  A9 02     LDA #$02       A:02 X:00 Y:00 F:20 S:1ff Cycles=2
1006  85 91     STA $91        A:02 X:00 Y:00 F:20 S:1ff Cycles=3

Here is a chart of the resulting timing of the instructions that cross page boundaries and/or are affected by the decimal flag:

A black & white pdf version is attached here:

cycle counts.pdf

(314.05 KiB) Downloaded 180 times

I am attaching the modified program, which carries version 1.2.6.1 for now.

6502.zip

(539.28 KiB) Downloaded 169 times

Thanks!

Daryl

[BigDumbDinosaur]

No reply from Mike Kowalski as yet.

[Dr Jefyll]

8BIT wrote:

Here is a chart of the resulting timing of the instructions that cross page boundaries and/or are affected by the decimal flag

For what it's worth, JMP (ind) and JMP (ind,X) also involve possible crossing of page boundaries.

This is wonderful work you're doing, Daryl. Thank you!

One other point has to do with 'C02 undefined NOP's. (Unlike undefined NMOS ops these are very simple.) Dunno if it merits your attention, or if the simulator even recognizes them, but some of those instructions *are* occasionally useful (as a trick to avoid coding a BRA instruction). Details here.

-- Jeff