Connecting a AY-3-8910 to the 6502 bus.

[Dr Jefyll]

Martin_H wrote:

I'm trying to use an LED on the board to monitor this I/O select, but I don't drive it directly.

You could drive it directly, you know. Tie the '138 output to the cathode of the LED, and the anode goes to the 1K (or smaller) resistor which in turn ties to +5.

When the '138 output goes active (ie, low) then the effect is to make the LED go bright, rather than go dim. But that's probably more easily perceptible, wouldn't you say?

Really you want a logic probe. But doing things by the seat of your pants can work, too!

[Martin_H]

I have a low quality logic analyzer* that I built from a kit. When it works it can detect high, low, and pulses. When it doesn't it becomes blinkenlights of disinformation.

But today must be the right phase of the moon because it shows pulse on the clock, ACIA select, and VIA select, with high always on /7F0x. So it looks like writes to address 7F00 and 7F01 don't bring pin 15 of the 74ls138 low. This is Rich Cini's version of Daryl's SBC-2. The schematics are here: http://sbc.rictor.org/sch2.html

Given that it selects /7F5x, /7F6x, ad /7F7x, I am not sure why the other pin isn't going low.

* It's an Elenco LP-525K that has reliability problems due to the poor quality of the PCB. I wrote Elenco a note saying that it was a piece of junk. Specifically the traces and pads are too thin, delaminate from the PCB at the drop of a hat, and fixing them with jumpers added noise and caused other traces to delaminate. It's mostly $15 down the drain.

[Martin_H]

The following program pulses the 74ls138 pin 15 (/7f0x) low:

Code: Select all

10 AY=$7F00
20 POKE AY, 0
30 GOTO 20

While I was at it I tested all the other pins and all work as expected. However, the LED doesn't pulse and I think the transistor can't switch fast enough for the brief time it is low. If I ground the input to the transistor the light does go off.

[GaBuZoMeu]

There could be a short circuit between p16 and p15 of the 138.

[Martin_H]

There's no short.

I think the problem is that the one transistor inverter won't switch when the 74LS138 goes low. While I can rework the LED to sink current directly to the 74LS138, I was using the one transistor inverter as part of the decode logic since I need 7f0x, not /7f0x. So I need a single inverter that will respond to the 74LS138.

This is your classic 2n3904 RTL inverter that I have used in many microcontroller projects. But never in a 6502 project.

[GaBuZoMeu]

Yes of course the transistor is too slow. But I understand your previous posts that this specific output (p15) won't go low, thats why a s.c. to Vcc could have been a simple reason.

As Dr.Jefyll said, you can connect the LED and a current limiting resistor directly to LS138p15. As the pulses are very brief you should use a high efficient LED (those that require only 1..2 mA for full brightness) but you should calculate the current limiting resistor to 10..15mA (that is much for the LS138) : 5V-1.8V (LED) - 0.5V (LS) = 2.2V => 220 Ohm.

Still you should avoid too much ambient light though.

[GaBuZoMeu]

I don't know whether you have a monitor program that allows you to run machine language programs directly. A short loop accessing $7F00 would help to make the signal more visible.

If you can enter somewhere in memory s.th. like $18 $AD $00 $7F $90 $FB and run this (starting at $18) it loops endlessly. It takes 7 cycles and 1/2 of that is where /CS7Fxx should be low. Thats a duty cycle of 1/14, should be just enough to be visible with your LED.

[Martin_H]

Thanks for the suggestions. I rewired the LED with a 1K resistor from 5 volts to the anode and the cathode to /7f0x. The LED was initially off, so I went into the monitor and did a STA 7f00 in a loop. The LED came on, so it works as an indicator.

Now I need to replace the 2n3904 RTL inverter with something that works. I had hoped to avoid another IC for a single not gate, but I guess not.

[GaBuZoMeu]

Nice to hear that it works
Probably I over read it - you require an active high select instead of the 74LS138 signal or why do you wish to replace the 2n3904 ?

[Martin_H]

I need an active high rather than an active low to AND with the clock. I ordered six NOR gates off a US eBay seller , so I should be back in business by mid-week.

[GaBuZoMeu]

The LS138 has 3 enable lines, 2x active high. If this does not collide with the other outputs you may use one of them. ?

[Martin_H]

This is the output of the 74ls138 which is fed into my select logic for the ay-3-8912. It was two inputs BDir and BC1 which need to be driven as I described above. I had a quad NAND gate which did everything except invert /7f0x. That's why I did the gingerbread transistor inverter, because I was fresh out of logic gates.

[Martin_H]

Today I added a real inverter and did some testing. When the computer is running, but no write to 7f0x is done, both BDIR and BC1 are low as expected. So far so good. When I write to 7f01 I see a pulse on both BDIR and BC1 which is expected. So far so good. When I write a zero to 7f00 I see a pulse on BDIR as expected, but I also see a pulse on BC1 which is not expected.

So two out of three ain't bad, but it isn't good enough in this case. I am a bit out of my depth because I don't have a scope, so I can't see the timing in detail to see what is going on. I just know that it is not doing the right thing.

I plan to do more debugging tomorrow.

[Martin_H]

This morning I double checked all the wiring and it matches the logic diagram. I also entered this test program in the monitor:

Code: Select all

0500 STA 7F00
0503 JMP 0500

BDIR is also working exactly as expected. When the program is not running BDIR is low, but when it is running BDIR is high. In a tight loop I would expect BDIR AND A0 (BC1) to always be low because any time BDIR is high, A0 should be zero. Instead I am seeing pulses on BC1 and this is really mysterious.

I am wondering if propagation delays are allowing BDIR to be high for a short time after the value of A0 has changed, and perhaps ANDing BC1 with the clock would fix that?

Other than that I don't have any ideas.

[Martin_H]

Good news and bad news. The good news is that adding A0 AND CLK made the BC1 line behave as expected. So my guess was correct. The bad news is that the program below should set the port A pins low, but doesn't:

Code: Select all

0500 LDA #$0E
0502 STA $7F01
0505 STZ $7F00
0508 JMP $0500

I will double check the wiring of D0-07, but it may be that D0-07 don't yet have the correct values when BDIR and BC1 transition to high. I looked at the 6502 timing diagram and those pins don't have their value until part way through CLK2, while the address bus does have a value. So that would cause BDIR and BC1 to go high, but junk data might latch rather than what I want.