Re: MOS6502 Release Schedule
Posted: Thu Jun 01, 2017 11:40 am
I might do some reading, to see what the current thinking is on EPIC - that's the architectural idea behind what became Itanium. I did find this:
I'm assuming I'll find that the current thinking is that EPIC was a mis-step. But who knows. Certainly Itanium are enormous chips: there's the question of performance, but also price, and power. And the question of verification - complex designs are difficult to get right, which makes them expensive to develop, or late, or buggy, or some combination.
Quote:
The designers of RISC CPUs realized that most people coded in some compiled language. They then realized that it did not make any sense to use valuable chip space for instructions and addressing modes that language compilers were not going to use. It's like selling toilets to people that don't have pluming.
EPIC, on the other hand, tries to address something very different. Superscalar CPUs have been around for quite some time now. There are two big problems in designing a superscalar CPU. The first problem is in deciding which instructions can be executed in parallel. Huge amounts of chip space in both the Alpha 21264 and the PentiumII are dedicated to this task. The second problem is in finding enough instructions that can be executed in parallel. Most C code results in a branch instruction after an average of five sequential instructions, and this makes it impossible to make most code run in parallel. Digital, Intel, and others have spent huge amounts of chip space trying to solve this problem too. These are the problems that EPIC tries to solve.
Instead of having the CPU guess at what instructions can be executed in parallel, EPIC requires that the compiler explicitly tell the CPU which instructions can execute in parallel.
EPIC, on the other hand, tries to address something very different. Superscalar CPUs have been around for quite some time now. There are two big problems in designing a superscalar CPU. The first problem is in deciding which instructions can be executed in parallel. Huge amounts of chip space in both the Alpha 21264 and the PentiumII are dedicated to this task. The second problem is in finding enough instructions that can be executed in parallel. Most C code results in a branch instruction after an average of five sequential instructions, and this makes it impossible to make most code run in parallel. Digital, Intel, and others have spent huge amounts of chip space trying to solve this problem too. These are the problems that EPIC tries to solve.
Instead of having the CPU guess at what instructions can be executed in parallel, EPIC requires that the compiler explicitly tell the CPU which instructions can execute in parallel.