Few questions about my plans

[cbmeeks]

GARTHWILSON wrote:

The duty cycle will be 50%, even if the oscillator's duty cycle is not.

@pogof,

You will be doing yourself a great service by listening to these guys. They actually do this stuff professionally. ;-D

One thing Garth is saying, if I understand correctly, is that sometimes components don't have a perfect 50% duty cycle and by running them through flip-flops, counters, etc., you are "squaring off" the signal.

[pogof]

@GARTHWILSON I am little bit confused right now. ( I think) I know that there is difference between these two types. But it still doesnt make any sense. I konw that 6502 have CLOCK input. So for that I bought 2MHz (the 4 leg) oscillator. But the TMS9918A have XTAL1 and XTAL2 inputs like on Arduino for example. So I think I need 10.7(whatever the number is) MHz (2 leg) crystal and two 32pF (or what the datasheet for that crystal specifies). And only thing I was able to source was the 21. ...MHz two pin crystal. If I can use something else how that would be wired up?

[GARTHWILSON]

What I see in your data sheet is very strange. When you see two pins connected to a crystal like that, one is input and one is output. In that case, you can connect the external clock source to the input and leave the output unconnected. So I was looking to see which one is input, but they don't tell. One of them is apparently bidirectional, and on pages 59 and 60 of the .pdf file, they tell how to connect an external clock source. If you want to do that with the FF, connect its Q output to one XTAL pin and the Q\ output to the other XTAL pin. Their diagram shows an extra inverter's delay between the two. If that turns out to be important, you can use just the Q output (connected directly to the XTAL1 pin) and run an inverter between it and the XTAL2 pin. I don't know why they have the 470-ohm pull-up resistors there unless they expect an open-collector inverter. They did not specify though.

[cbmeeks]

I would also like to suggest studying the schematics for some of the legacy systems that used the TMS9918 chip.

For example, the ColecoVision, TI-994/a and many others used it so their schematics may help you understand how that chip was used in actual products that sold millions of units.

[BigDumbDinosaur]

cbmeeks wrote:

One thing Garth is saying, if I understand correctly, is that sometimes components don't have a perfect 50% duty cycle and by running them through flip-flops, counters, etc., you are "squaring off" the signal.

That's correct.

Most can oscillators' output is very close to a 50 percent duty cycle but does exhibit a tolerance. For example, the ECS 2100 series oscillators I use in POC have a typical output symmetry of 50 ±3, with the extremes being 45-55. At low speeds, some Ø2 asymmetry is tolerable (and, in fact, can be taken advantage of in some cases), but as Ø2 closes in on the 14 MHz official maximum of the WDC MPUs, asymmetry may result in subtle timing violations that could spell trouble. Jeff Laughton (Dr. Jefyl) illustrates this phenomenon in his timing diagram explanation on his website.

Running the oscillator output through a flop not only guarantees true symmetry it usually produces a stronger clock signal. In most cases, the flop should be a 74AC74 or 74ABT74. Both produce an output transition time that is well within the recommendations for the WDC MPUs, as well as plenty of source and sink current.

[pogof]

@GARTHWILSON Ok that is the information that I was missing all along. So I can use 10.7...MHz source or divide the 21. ...MHz in two and feed that to the XTAL input on that chip (in nutshell). But because I am not able source any of that I am out of options. @cbmeeks will hopefully send a 10.7 ...Mhz two leg crystal so that is the best option for now. I can try to experiment later when I get my hands on oscilloscope and I can control what I do.

@cbmeeks I will read through that on weekend when I have time. This just did not felt right but I now get what garath and BDD were trying to say.

@BDD that is good to know. This is just 2MHz job so I dont think that I will deal with any of that. T will read though that also on weekend.

The eeprom programmer arrived yesterday they didnt noticed on customs (that is like a miracle). That is shifting my plans little bit but I need to make the foundation first.

[cbmeeks]

@pogof

I discovered I have about 13 of those crystals.

I will be sending you 6 of them today. I have no idea how long it will take to get there. But it should go out today.

Enjoy!

[pogof]

cbmeeks wrote:

@pogof

I discovered I have about 13 of those crystals.

I will be sending you 6 of them today. I have no idea how long it will take to get there. But it should go out today.

Enjoy!

Thank you very much! Do you want enything?

[cbmeeks]

pogof wrote:

Thank you very much! Do you want enything?

Nah, just pay it forward one day.

[Dr Jefyll]

GARTHWILSON wrote:

What I see in your data sheet is very strange. When you see two pins connected to a crystal like that, one is input and one is output. [...] I don't know why they have the 470-ohm pull-up resistors there unless they expect an open-collector inverter. They did not specify though.

It is strange. I'm reminded of a clock circuit Commodore uses for driving the 6509. There, too, we see low-value pullups attached this way. The gates in the Commodore circuit are just the usual totem-pole type (ie, not open-collector), so it's pretty clear the job of the resistors is to raise the logic-high voltage. (TTL Voh falls short of the spec required for the 6509 clock inputs.) Still, I don't see how or whether that reasoning can explain the pullups in the 9900 circuit on page 60 of the PDF.

BigDumbDinosaur wrote:

In most cases, the flop should be a 74AC74 or 74ABT74. Both produce an output transition time that is well within the recommendations for the WDC MPUs

Certainly 74AC74 is appropriate, but 74ABT74... not so much. Again there's the problem that TTL output levels fall short of what's required by the inputs of the device being driven. (Spec's for WDC CPU's indicate that none of the inputs -- clock or otherwise -- accept TTL levels.)

It's something we all need to be aware of. In the past it was fairly safe to assume any part that's CMOS will feature rail-to-rail swings on its output pins. Good times! But, unfortunately, modern CMOS parts may or may not feature rail-to-rail output swings -- you have to check the Voh spec. in the datasheet. Families such as 74HC, HCT, AC and ACT can be implicitly trusted in this regard, but otherwise you need to check.

If the Voh of your gate fails to meet the Vih spec of the gate it's supposed to drive then your project will either...

• work
• not work, or
• fail at unpredictable -- and usually inopportune -- times!

-- Jeff

PS: the 'ABT74 is actually a "BiCMOS" part. NPX's datasheet says Voh can be as low as 2.5V. (That's when sourcing 15 mA. At lower currents we can perhaps expect a somewhat higher voltage, but the datasheet offers no assurance of this.)

[BigDumbDinosaur]

Dr Jefyll wrote:

BigDumbDinosaur wrote:

In most cases, the flop should be a 74AC74 or 74ABT74...

Certainly 74AC74 is appropriate, but 74ABT74... not so much. Again there's the problem that TTL output levels fall short of what's required by the inputs of the device being driven.

Yes, I should have noted that. In most of our stuff, which would be CMOS operating on a 5 volt supply, the 'AC74 would be the appropriate choice.

Quote:

(Spec's for WDC CPU's indicate that none of the inputs -- clock or otherwise -- accept TTL levels.)

If you recall, we had a topic going about this. The conundrum was why do the WDC MPUs, which, according to the data sheets, see only CMOS levels as valid inputs, work with devices whose data sheets say produce TTL outputs. For example, consider the ISSI IS61C1024AL 128Kb × 8 SRAM I used in POC V1.0 and POC V1.1:

Code: Select all

Voh   Output HIGH Voltage   Vdd = Min., Ioh = –4.0 mA   2.4   —   V

Going by that, the 65C816 wouldn't recognize a high output from the SRAM as a valid logic 1. Yet it does. Ditto for the Cyrpress 512Kb × 8 SRAM Garth uses in his 4MB DIMM. It shouldn't work, but it does.

[Dr Jefyll]

BigDumbDinosaur wrote:

Going by that, the 65C816 wouldn't recognize a high output from the SRAM as a valid logic 1. Yet it does. Ditto for the Cyrpress 512Kb × 8 SRAM Garth uses in his 4MB DIMM. It shouldn't work, but it does.

Agreed, and I've gotten away with this myself. But let's be clear about what we mean when we say it "works."

There's clearly a loss of noise immunity. The project will have less margin to tolerate degraded logic levels, which can result from factors such as

• ringing, ground bounce, and excessive loading
• reception of external magnetic, electrostatic and RF fields

. External fields can be a problem anywhere, but in industrial and automotive environments the hazard is usually severe.

Another point is one Garth raised in the linked-to thread, and it was an eye-opener for me. The chip might not achieve its full speed potential if the logic levels at its inputs fall short of spec.

GARTHWILSON wrote:

CMOS gates tend to have a pretty high gain, so there's almost no "no-man's land" around the threshold voltage (which is usually half Vcc). However, there's the problem that the propagation delay through the gate will be much higher if the input goes only a little way into the opposite logic level. IOW, getting the specified speed performance will require getting the input more than just a little way into the logic "1" area. I suspect that's where the 70%-of-Vcc spec comes from. It's not that 52% doesn't qualify as a "1", but that you have to get to 70% for the speed guarantee to be valid.

[pogof]

Ok so update about the project!

I was busy with school but now I will have a little bit of free time to work again on the project. I was shopping for parts last week, bought some components that I was lacking of and so on. Olso Now I have a general idea of how should I make the computer working, I read the primer and some other resouces.

I now have board with sockets attatched to it (I should started from breadboard, oh well ) and I will wire it all up one by one and always test if the bit I wired up is working. How the layout will work out in the end I really dont know, but I tried to minimalize the lenght of all connections. I will start from the point to point connections and simple circuits and make my way to the buses. First I wired up a reset circuit that I found here: http://www.grappendorf.net/projects/650 ... rcuit.html . It should be Commodore 64 direct copy so I will trust it. Now I going to wire the decode logic (same as in primer) and VIAs.

Wireing is the easy part, the worse part is the programming. I dont know anything about it. I read something about it but I dont remember anything .

I put the image of the layout as attachement. If you find that some important IC is missing, daughter board will have to cut it.

(P.S. Can the title of this thread be changed after I come up with name for the system? I think that the title will not correspond to the content from this point on.)

[GARTHWILSON]

Let me point you again to the 6502 primer, the page on reset circuits at http://wilsonminesco.com/6502primer/RSTreqs.html where you will find simpler ones, and also the page on how to start writing your software, at http://wilsonminesco.com/6502primer/PgmWrite.html . What you show there is breadboard. It's just that it's not solderless breadboard. If you're able to wire-wrap, you will find it easier and more reliable than soldering wires, and you can get the highest density and shortest connections. See the 6502 primer's chapter answering wire-wrap questions and doubts, at http://wilsonminesco.com/6502primer/WireWrap.html . Actually, the primer is set up in a logical order, so going through from beginning to end is best. If you just skip around, you'll miss important things.

[Vladimir]

Hi pogof.
I am busy with something as you at the moment. I have installed connectors beside VIA and ASIA IC's (for ribbon cables with IDC). I think, it is more comfortable than floppy soldered wires around board.
I also do not see in your design any kind of line driver and receiver for ACIA (75188 and 75189 for example). Are you planned serial port with TTL levels, for short distances?

Cheers
Vladimir