6502.org

The SRAMs I've worked with don't care what OE\ is when they're not selected or when WE\ is low.

The SRAM chip select will depend on more than just phase 2 since you don't want the SRAM to be driving the bus when you're trying to read I/O or ROM.

I recommend that you verify that against the data sheet for the specific SRAM you are using. While in most cases such an arrangement will work, it's not wise to assume so.
Ø2 should not be used to quality chip selects (especially so with the 65C21, 65C22 and 65C51). You should qualify RWB with Ø2 and gate CE strictly by your memory decoding logic. Doing it as you are doing it results in part of the Ø2 high cycle being wasted as the SRAM responds to /CE being asserted.

I checked my SRAM datasheet and its truth table reports Don't Care for OE so I should be good to go.

I visited my local electronics shop today to get a 628128 chip (128k x 8 SRAM) to replace my 32k SRAM but they didn't have one on the shelf. Instead I got a 70ns KM681000 which is supposed to be completely compatible with a 628128. I wonder why it isn't called "628128" then, if there is no difference. *shrugs*

I'll get back to you on the phi2 stuff later -- I have a somewhat unorthodox setup which is better explained with a schematic (which is only in my head at the moment!).

Anyway, I can now toggle between 1 Mhz clock signal and single-stepping on the fly without crashing the 6502 *huzzah!*
I.e. I can pause the 1 Mhz clock reliably on high state and switch to single-stepping and then back to the 1 Mhz clock.

The clock and reset signals are generated by the AVR, so I can easily choose between 250 khz, 500 khz, 1 Mhz, 2 Mhz and 4 Mhz clocks by updating the AVR firmware. I'm planning to make the clock selectable with a rotatory or DIP switch.