Recommendations for a ROM chip that will work at 10Mhz?

[BigDumbDinosaur]

LIV2 wrote:

Thanks again, after reading the thread on high speed digital design and I don't think I'm going to get near 10Mhz anyway.

It'll depend a lot on physical layout and construction techniques, as well as prop delays through the logic. When I designed my POC V1.0 unit, a primary goal was the achievement of 8 MHz operation. I met that goal by some 50 percent, as V1.0 could run at 12.5 MHz, using 74AC logic. Attaching the SCSI host adapter (HBA) forced me to run the unit at a slower pace (10 MHz), as the HBA effectively took the MPU's buses off the board and significantly increased bus loading.

Quote:

The reason for that is that my design will use ISA style connectors for peripherals connected to the cpu bus, and as I understand it'll be too noisy to get above a few mhz, not really an issue though since I'm just doing this for fun and probably won't be able to tax the system enough to need that much speed, at least for a while.

Have you considered employing the socket used for PCI cards? It's a more compact design than the old ISA-style socket, and has been specifically designed for higher frequency operation.

The 32 bit PCI standard, the most commonly used in x86 machines, clocks the bus at 33 MHz, so we know those connectors are up to it. Of course, the PCI bus is not directly attached to the MPU's buses like the old VESA local bus (VLB) was, so PCI cards can't load down the MPU. You may find yourself using bus drivers to get reasonable performance and stability.

socket_pci_molex.pdf

Molex PCI Socket

(108.25 KiB) Downloaded 123 times

[LIV2]

Brilliant idea, I'll get my hands on some PCI Slots!

Bus loading is something I hadn't considered enough, though I'm told the W65c02 can drive a lot more than the old NMOS chips I'm sure I'll still need to make sure each of my cards is buffered

My current design has CPU, RAM and ROM on the one board, which will then plug into a passive backplane. I'm thinking that it should be fine provided the buffers I use are fast enough, the only other concern there becomes bus termination as far as I can tell, though I'm a newbie at this so there's probably a whole lot of things I'm missing.

[BigDumbDinosaur]

LIV2 wrote:

Brilliant idea, I'll get my hands on some PCI Slots!

Sometimes I fool humans with my smarts routine.

Quote:

Bus loading is something I hadn't considered enough, though I'm told the W65c02 can drive a lot more than the old NMOS chips I'm sure I'll still need to make sure each of my cards is buffered.

It is true that the W65C02S and W65C816S can drive the buses harder than the NMOS devices. However, the data sheets don't really say just how hard—their numbers are always suspect. For example, the data sheets say output currents are 700/1600 microamps at 5 volts. Yet experience suggests that the numbers are much higher than quoted. If that 700/1600 number were really true my POC V1.1 unit would not function at the speed (12.5 MHz) at which it is running.

Quote:

My current design has CPU, RAM and ROM on the one board, which will then plug into a passive backplane. I'm thinking that it should be fine provided the buffers I use are fast enough, the only other concern there becomes bus termination as far as I can tell, though I'm a newbie at this so there's probably a whole lot of things I'm missing.

One step at a time. You should build a simple working unit that doesn't take the buses off-board so you can get your feet wet. As soon as you introduce a backplane you may introduce all sorts of potentially intractable problems. Slots on the mainboard, driven from a buffered I/O bus, while technically more challenging to design, has a much greater likelihood of succeeding.