6502.org

Code: Select all

// timing parameters
parameter 
    HFRONT  = 2,			// front porch (+right border)
    HVIDEO  = 1024,		// active video area 
    HSYNC   = 2,			// hsync 
    HBACK   = 318;		// back porch  (+left border)  :1346 horizontal pixels total 356

......

//horizontal & vertical delay using a multi-stage single bit shift register
parameter hvd = ((HFRONT + HVIDEO + HSYNC + HBACK) * 22) + 11;		//22 scanlines + 11 pixel delay
	
reg [hvd:0] s;

wire q = s[hvd];

always @(posedge clk)
   s <= { s[hvd-1:0], countflag }

......
......

//X & Y pixel counters
reg [9:0] X = 0;
reg [9:0] Y = 0;

always @(posedge clk) begin
		if ( vstart | ( X == 1023 & Y == 767 )) begin
			X <= 0;
			Y <= 0;
		end
		if ( X == 1023 ) begin
			Y <= Y + 1;
			X <= 0;
		end
			else if ( q ) 
				X <= X + 1;
end;

Code: Select all

//delay countflag
parameter hd = ((HFRONT + HVIDEO + HSYNC + HBACK) * 11) + 4;		//11 scanlines + 4 pixel = 1346 cycle horizontal delay
	
reg [11:0] s = hd;			//delay down counter
wire hd_done = s[11];		//delay count done
reg q;							//delayed output

always @(posedge clk) begin
   if (countflag)
		s <= s - 1;
	if (hd_done) begin
		q <= !q;
		s <= hd;
	end
	if (!countflag)
		s <= s - 1;
end

Code: Select all

// adjust down counter. Reload when it's done.
always @(posedge clk) 
	if( venable ) begin
	     if( VSYNCin | vcount_done )
		  vcount <= { 1'b0, vload };
	     else
		  vcount <= vcount - 1;
	end

// when down counter is done, go to next state
always @(posedge clk) 
	if( venable & vcount_done ) 
			case( vstate )
				VIDEO : vstate <= FRONT;
				FRONT : vstate <= SYNC;
				SYNC  : vstate <= BACK;
				BACK  : vstate <= VIDEO;
			endcase
		else if (VSYNCin)
			vstate <= VIDEO;

Code: Select all

//delay countflag
parameter hd = ((HFRONT + HVIDEO + HSYNC + HBACK) * 11) + 4;		//11 scanlines + 4 pixels = 1346 cycle horizontal delay
	
reg [11:0] s = hd;			//delay down counter
wire hd_done = s[11];		//delay count done
reg q;							//delayed output

always @(posedge clk) begin
   if (hd_done) begin
		q <= !q;
		s <= hd;
	end
		else if (countflag | !countflag)
			s <= s - 1;
end

Code: Select all

//pixel counters & video address
always @(posedge clk) 
	if ( hstart )
		countflag <= 1;
	else if ( hblank )
		countflag <= 0;

Code: Select all

//delay countflag
parameter hd = ((HFRONT + HVIDEO + HSYNC + HBACK) * 11) + 4;      //11 scanlines + 4 pixels = 1346 cycle horizontal delay
   
reg [11:0] s = hd;         //delay down counter
wire hd_done = s[11];      //delay count done
reg q;                     //delayed output

always @(posedge clk) begin
   if (hd_done) begin
      q <= !q;
      s <= hd;
   end
      else if (countflag | !countflag)
         s <= s - 1;
end

Code: Select all

always @(posedge countflag)
.....delayed output reg will go high after many cycles
.....
always @(negedge countflag)
.....delayed output reg will go low after same amount of cycles
.....