Page 2 of 3
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Tue Feb 19, 2013 7:17 pm
by ElEctric_EyE
Also, with:
Code: Select all
...AA STA ($0000),Y ;$8000_0000 begin videoRAM
INC A
DEY
BNE AA
...
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Tue Feb 19, 2013 9:09 pm
by ElEctric_EyE
An interesting observation:
Writing all blue pixels ($001F) to the videoram results in a almost 100% blue screen with different shades of blue present.
Writing all green pixels ($07E0) results in 100% green.
Writing all red pixels ($F800) is horrible, with different shades of red.
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Tue Feb 19, 2013 9:34 pm
by Arlet
Does it get worse if you put your finger on the signal wires ? Could be a timing issue. Your code assumes the data is ready on the next cycle, but that ignores the IO buffer and trace delays. That's why in my SRAM code, you'll see that I wait an extra cycle before using the data from the bus (that was at 100 MHz using 10 ns SRAM):
Code: Select all
always @(posedge clk) begin
ch1_valid_1 <= (state == VGA1);
ch1_data_valid <= ch1_valid_1;
end
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Tue Feb 19, 2013 10:54 pm
by ElEctric_EyE
Arlet, I'll check this out tomorrow and see if I can experiment with the IOB delays, maybe change the slew_rate or do what you have done.
Here are the files needed to create the project, it should run on the board you have. I have a feeling my RST.v circuit does not last long enough because after shutting down power to the board and powering back up, red is much more consistently random. More experiments are needed...
Just note the SYSROM looks for the .coe file in a specific folder as spec'd by the 'initial' statement in SYSROM.v. You or anyone else might need to change it to run a good simulation. The "REGFILE_INIT.COE" file should be put inside the Xilinx project file folder.
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 10:20 am
by Arlet
I don't have that SRAM chip yet, so I can't test it on my board. I do recommend using some more of my code. It also has a state machine that keeps track of sharing the SRAM with CPU/Video, which also deals with bus turnaround times (going from read to write you need to wait a cycle so the SRAM chip has a chance to set the outputs to high-Z state).
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 10:37 am
by ElEctric_EyE
I'll try that. BTW I've checked for that RAM availability, and they are hard to find in stock. DigiKey has though.
So I'll start by trimming out the parts with 'ch1' since that deals with another external ram that is read only. How should I go about re-ordering the state machine?
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 10:45 am
by Arlet
No, the ch1 parts are what you should use for video output. It's a read-only data channel. The ch2 parts are for the CPU, and it provides separate read and write channels. The state machine is fine too. All you need to do is get rid of the ram_ce2, and ram_d2 and bank signals, and only use the ram_ce1 and ram_d1 signals. So, this:
Code: Select all
always @(posedge clk)
read_data <= bank_1 ? ram_d2 : ram_d1;
Should be:
Code: Select all
always @(posedge clk)
read_data <= ram_d1;
And of course, my code targets an async SRAM, and you're using a synchronous SRAM.
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 11:21 am
by ElEctric_EyE
I was thinking before I tackle your code, right now I am using a single output of a PLL. Ive just modified it to have 2 outputs: 1 for cpu and 1 for pixel clock. Same frequencies, but different phase. I know it's lazy, but I've not had my coffee yet.
Either way, I think it is almost time for a FIFO thread. I am eager to learn!
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 12:30 pm
by ElEctric_EyE
I quickly see, a simple phase delay is not going to work, so more questions on how to merge your code into mine.
Must your module be merged into my top_level module since it has an 'inout' port? or should it be it's own module and I just route the 'inout' wires to the top_level?
Do I have to adhere to the separate read and write addresses in your module?
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 12:38 pm
by Arlet
You can keep it as its own module, and just route the inout wires higher up. The tools are smart enough to figure out what to do.
If you only need a single, common read/write address, you can easily modify the code to only use a single variable. Alternatively, just define a single address in the top level module, and hook it up to both the read and write address ports on the sram module. That way you don't have to change anything, and you can always use separate read/write addresses later, for instance if you wanted to include a DMA controller.
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 1:24 pm
by ElEctric_EyE
Ok, I think I almost have it. 1 more question: Since I use only 1 RAM and it's always selected, can I safely discard the following?
Code: Select all
always @(posedge clk)
if( next == READ1 || next == VGA1 || next == VGA2 ||
next == READ2 || next == WRITE1 )
begin
ram_ce1 <= 0;
ram_ce2 <= 0;
end else begin
ram_ce1 <= 1;
ram_ce2 <= 1;
end
always @(posedge clk)
ram_oe <= ~(next == VGA1 || next == READ1 ||
next == VGA2 || next == READ2 );
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 1:28 pm
by Arlet
You can discard the CE signals, but you'll need the OE.
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 1:35 pm
by ElEctric_EyE
uh-oh, an oversight. I believe I have it hardwired to ground on the board.
Maybe will have to create another 'Z' bus inside the FPGA?
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 2:00 pm
by Arlet
You may be able to work around the missing OE. I don't have the datasheet in front of me, but I would expect you can turn the SRAM outputs high-Z using the WE signal instead. In that case you can do this:
cycle #1, WE deasserted, reading from SRAM, FPGA high-Z
cycle #2, WE asserted, FPGA-Z, SRAM turns high-Z
cycle #3, WE asserted, FPGA writes data.
In cycle #2 and #3 you should keep the address the same. In cycle #2 you write random data, and then in cycle #3 you overwrite it with the correct data.
The Spartan-6 does not have internal signals that can go high-Z. Only the IO buffers have that capability.
Re: Interfacing external RAM to a Xilinx FPGA using Verilog
Posted: Wed Feb 20, 2013 2:15 pm
by ElEctric_EyE
Thanks for your patience! I have an active high CS which is connected and can be used similar to an OE according to the truth table, so I'll just make that substitution.
Also, your module needs another modification, since I need zeroes going to the cpuDataIn when not selected, would I use
for the logic to pass the data, else all zeroes?