Beginners CPLD

8BIT · Post by **8BIT** » Sat Dec 03, 2011 3:15 am

Dajgoro wrote:

Well, i bought four XC9536, and sockets. I also managed to install ISE, now i just need to figure out how to transfer the program to the cpld using the lpt port...

I wrote a detailed instruction for that for someone else. I'll see if I can find it and post it. Basically, after you compile the logic, you open the impact tool inside of ISE and it will send the programming to the parallel port through the progamming adapter, and to the CPLD.

Daryl

8BIT · Post by **8BIT** » Sat Dec 03, 2011 4:29 am

Found it. Here it is:

Code: Select all

Some notes first.
You DO need to power the target board from your own supply.  The JTAG Gnd and Vdd pins are used to power the IC in the adapter, not to power your target board from the parallel port

Also, you should be able to use impact, as that's what I do, as long as you have a parallel-3 compatible cable.

You may want to double check the schematic of your JTAG header to ensure its functions line up correctly.

My pinout from the programming adapter is as follows:

1 +5v from target board
2 gnd
3 tclk
4 tdo
5 tdi
6 tms


Here are the steps I use:

1) compile the source to generate the JED file.

2) open the impact under the generate Programming file tab of the ISE - > Configure Device

3) select configure device using boundry scan (JTAG) - click finish

4) if the programmer is powered and the XC95xxx connected, you should get a simple schematic showing TDI, the XC95xxx, and TDO.

   if not, then it will report trouble.  not powering the target board will also land you here.

5) right click on the xc95xxx, and select program

6) it may ask you to verify the JED file, and ensure "erase device before programing" is selected

7) should take about 20-30 seconds total to erase, program, and verify.

Hope that helps once you get the logic written and the programmer build.

Daryl

Dajgoro · Post by **Dajgoro** » Sat Dec 03, 2011 4:35 am

Thanks, now have to build the programmer, and wait for the cpld to arrive...
This topic might be seen as a small cpld tutorial for beginners.

Nightmaretony · Post by **Nightmaretony** » Mon Dec 05, 2011 3:26 pm

A little bit of a worry, am going to use a Xilinx XC95108 for the pinball mind gating logic. Digikey lists all j wing versions as non stock. Trying to avoid SMD, period. this chip is easily still available though and doesn't seem to go EOL? If it is headed towards oblivion, what through hole 5 volt alternatives are recommended?

also, some low level tutorials linked would be sweet, going to be the first time using CPLDs

ElEctric_EyE · Post by **ElEctric_EyE** » Tue Dec 06, 2011 12:14 am

All Xilinx 5V CPLDs are EOL.

Their 5V input tolerant FPGAs went first, but Spartan 2 is still being produced IIRC, although you will be forced to use ISE 10.1 or earlier for development.

I would recommend, if you are using 5V CMOS for input circuits, 3.3V Xilinx CPLD/FPGA switching levels may be sufficient. For 5V CMOS/TTL output circuits, you will need a 5V input tolerant CPLD/FPGA, i.e. Coolrunner II XPLA3/Spartan 2 respectively. I think they're the only ones left!

Good luck! And if you really want to aim for the future aim low, as in volts...

Nightmaretony · Post by **Nightmaretony** » Tue Dec 06, 2011 12:52 am

bleah. Already laying out the board for the XC9500 series. Am putting pins all around to create an adapter board. Sigh. trying to make the entire circuit 5 volts and keep it that way

can use a coolrunner I guess on an adapter board and keep using what stock I can find of the xc9500 series.

thanks!

ElEctric_EyE · Post by **ElEctric_EyE** » Tue Dec 06, 2011 12:59 am

Nightmaretony wrote:

...Sigh. trying to make the entire circuit 5 volts and keep it that way

...

What is so important for 5V operation in your circuit?

Nightmaretony · Post by **Nightmaretony** » Tue Dec 06, 2011 5:19 am

The eproms and rams are 5 volts and it runs a 5 volt piggyback to a pinball machine. it uses what I nickname as forever technology as you can find certain chips while others die. I also have literally thousands of eproms new I can use for this project. UYnless there is an easy and cheap way to 2 way buffer down to 3 volts and rebuffer back to 5 volts, as the board breakout runs through 74hc245 buffer chips.

http://www.nightmarepark.com/6502.php?d ... ll%20Mind/

look at the schematic and the 3D of the board.

But basically, a Coolrunner ][ would run 5 volt logic? I can deal with it being SMD, I set up headers to break out all the signals to a sub board if the cpld went EOL, which it did.

[EDIT] While Digikey lists the XC series as nonstock it IS available though. Still glad for the design decision to put breakouts for a sub board unto that day.....have a board with level shifters and all, ti should work out...

ElEctric_EyE · Post by **ElEctric_EyE** » Tue Dec 06, 2011 1:43 pm

Nightmaretony wrote:

But basically, a Coolrunner ][ would run 5 volt logic?

The only Coolrunner II that are 5V input tolerant I am aware of are the XPLA3 Family. If you see the XL suffix on a Coolrunner II device it is strictly 3.3V.
Sorry for the bad news.

Nightmaretony · Post by **Nightmaretony** » Tue Dec 06, 2011 3:50 pm

No worry. am sticking to the original plan for now, use the older XC series and design a sub board when I can't get them anymore....

http://www.nightmarepark.com/6502/Pinba ... d%203D.jpg

the square of headers around the CPLD would go up to a new CPLD sub board when required...

Karatorian · Post by **Karatorian** » Sat Feb 11, 2012 4:34 am

I'm a beginner interested in CPLDs as well and was wondering who's tools have the best Linux support. Any un*x users care to comment?

BigEd · Post by **BigEd** » Sat Feb 11, 2012 8:56 am

Can't speak of the other choices, but Xilinx tools work well on linux.

Only one caveat: if you're using a Xilinx USB-jtag adapter you may need to run a 2.6 kernel, such as can be found with a Fedora or a Redhat-style distribution. I tried the other day to get this working on an Ubuntu distribution with a 3.0 kernel and didn't succeed. (It might be possible though.)

There's no such limitation with a parallel-port adapter, but note: if you're using a parallel-port-jtag adapter, you need a computer with a parallel port. The USB-printer-port converters are not suitable for jtag.

Cheers
Ed

Arlet · Post by **Arlet** » Sat Feb 11, 2012 10:18 am

I am using Ubuntu 10.04 LTS (2.6.32 kernel), and I've got both the Xilinx Platform Cable USB II working, as well as the cheaper digilent USB cable. The Xilinx cable works seamlessly with the ISE software.

BigEd · Post by **BigEd** » Sat Feb 11, 2012 10:59 am

Good point - I've got an Ubuntu 10.10 here which is on a 2.6 kernel. But my usual machine has moved forward just a step too far.

Dajgoro · Post by **Dajgoro** » Wed Jul 25, 2012 3:35 am

As of my recent progress int he Minimalistic CPU topic, and since i got my LPT JTAG from ebay, i decided to wire up a XC9536 that is is supposed to control stuff around my sbc. So i soldered it, connected the jtag, and power. Then i went into ISE (13.3) and i took a AND gate and placed 2 inputs and 1 output, named it AIN1, AIN2, AOUT1. I took the datasheet, looked at the pins, and figure out that i like the pins 2, 4, 6, and that meant D6, C6, B6. I typed that into the ucf file, and hit that green button. And i got errors saying: (signal) is assigned to an invalid location ('(pin)') for this device. This will prevent the design from fitting on the current Device. (signal) must be reassigned before attempting a re-fit.
Then i started Pace, and he offered me only two pins FB1 and FB2, so i took them, but the error kept appearing. Then i ran an example using the xc9572, and that worked fine, the i switched it to XC9532XL, and it worked again, but when i selected the xc9536, i got the error again. Impact won't even open in this small project of mine, and when i open it using other projects, i get only errors, and red text. I tried googling, but that didn't go far... What i am doing wrong?

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