6502.org

Very nice!

Hi Andrew - this is a 5V tolerant part, I think? That's handy. My a5602 project (inspired by cjb's stm6502[1]) runs on a cheap ARM SoC board, which has many 5V tolerant I/Os, but is rather bulky.

It might be interesting to run your benchmark - it looks like it's this one: http://mdfs.net/Docs/Comp/BBCBasic/BenchMrks2 - is that so?

Cheers
Ed

[1] viewtopic.php?f=8&t=2177

Its a 3V3 device but some of the I/Os are 5V tolerant. How many do you need?

Yes thats the bench mark I'm using. I can't do the recursive part with 8K of RAM but I think the device may be able to support 16K of emulation memory - There is a discrepency between the data sheet (16K) and the memory I can see in the debugger (18K). I need to change a couple of macros and rebuild to test it out.

And I think I might try a little overclocking as well - See how far I can push it.

I've made all the code available as a SourceForge project

https://sourceforge.net/projects/em-65c02/

That's great, thanks!

A short video showing my VT220 shield and 65C02 emulation working together to run a simple BBC BASIC program.

https://plus.google.com/u/0/11755257763 ... cbhb7P7w6a

I've increased the RAM available to the emulation to 15K on the same device (wrapped at the 16K boundary). The area above the 15K ($3C00-$3FFF) is shared with the CPU stack.

Does that offer the amusing possibility of escaping the emulation by smashing the stack?

It does at the moment but I think I'll move the stack below the RAM in the next build then it the end area will map onto ROM which will put a stop to that.

I think I can also squeeze another 3/4 of a K into the RAM area so only a single 256 byte page is reserved for the host device.

Very nice demo', Andrew. Keep up the good work...

Cheerful regards, Mike

Having reached the limits of the Microchip 24F/33F chips (for the time being). I've been porting my emulation to a PIC32MX device and expanding the range of devices handled. I now have a 65C816 emulation with 128K of RAM and an 8080 with 64K.

I'm using a uJet32+ module http://www.ebay.co.uk/itm/PIC32MX795F51 ... 5278wt_981 which has a micro SD socket.

I'm working towards being able to boot CP/M 2.2 in the 8080 emulator and considering designing my own surface mount board combining a PIC32 and a PIC24 running my terminal software to make a 'CP/M on a credit card' system.

Later this year Microchip are releasing a new range of PIC32MZ devices with 1M of flash ROM and 512K of RAM operating at 200MIPS (the MX is only 80MIPS) which will give my code a 2.5x speed boost. I should be able to emulate a 65C816 at ~10-12MIPS (maybe more).

Microchip appear to have finally released the PIC24EP512GP202-I/SP devices I have been waiting for and some are due to be delivered this week so I can test the latest version of my emulator with a full 32K of RAM, 32K ROM and an improved execution loop/interrupt handler that should be a little faster than the old code.

All you need is one 10K resistor, 2x 100nF cap, a 10uF tant. cap, a single chip (for £3.23) and 3.3 volts for a 6Mhz+ 65C02 system that can use the PICs peripherals (I/O, SPI, I2C, UART, etc.) with support for IRQs and NMIs. A cheap PL2303 module (from eBay) can be used to connect using RS232 and power the circuit.

I've moved the code to the new MPLABX IDE and will be restructuring the public SVN archive (to support trunks for MPLAB and MPLABX) before I upload the new code.

*Edit: Missed a cap off the component list.

Sounds great!
How does the emulated CPU see the peripherals - escaped opcodes such as WDM, or emulated memory-mapped I/O, or something else?

I use the 65C816 coprocessor instruction COP ($02) to access a small number of native code functions that do things like read/write memory and set/clear/toggle bits - much like the BBC's OSBYTE/OSWORD calls.

The simple implemention of OSRDCH in my MOS emulation is: Where IO_READ is defined as:

Thanks for explaining - seems like a fine idea to me. Modelling memory-mapped I/O can only slow things down. (I hope I hadn't missed a previous explanation)