However, it would probably be not much more difficult to place some sort of bi-directional bus transceiver on the '816 board to handle the DMA stuff.
Actually, it's not easy unless the two machines are phase-locked to each other (and, even then, you still need synchronization logic). Otherwise, you're essentially implementing a 4-phase asynchronous bus interface for both sides, plus bus arbitration logic in between them.
It's better to use some deep FIFOs, but they're pretty rare. So, with the Kestrel-1, I implemented a DMA interface using 74ACT595 shift registers. To work with the Commodore 64, you'd replace the shift registers with parallel registers.
However, even here, you still need:
(1) A means to synchronize the 6510A against the 65816's clock, which even if running at the same speed, may well be out of phase. (And, were I building this, you can bet I'll be driving the 65816 at 16MHz or faster.) A 4-phase asynchronous interface is ideal.
(2) A means to let the 65816 interrupt the 6510A unambiguously. (Relatively easy)
(3) A means for the 6510A to trigger an interrupt on the 65816.
(2) and (3) are used to establish communications between the two computers. (1) is needed to not blow either side up doing so.
This is an issue I've run into when initially considering designs for my Kestrel-2 computer. In subsequent designs, I've dropped the asynchronous bus design and instead am phase-locking the VGA and CPU (which means the CPU runs at 12.6MHz -- period. No means of up- or down-grading the speed).
