6502.org

You can do whatever you want! The question is how much compatibility you'd like to offer, and compatibility with what (because the 02 and the C02 are different here, I think.)

It's useful to have compatibility with test suites, too. But it's certainly possible to draw a line - it's possible even to say that the D flag does nothing.

Well, my equation can be implemented in 3 gates (two XORs and a NAND). That hardly seems over-complicated.

yes but sometimes my laziness is close to infinity so even the smallest things are too much effort for me at the time.

also i'm having a hard time seeing where the gates are supposed to go as my BCD circuit is not that clean.
but i'll try! i recently got another project much closer to completion so i'm still riding that high!
there are 4 seperate adders, 2 for each nibble/digit.
the input numbers and the carry input are on the left, and the output and carry output is on the right.

the first adder at the top left adds the 2 lower nibbles together, the carry output and the mess of AND/OR gates after that are to generate the carry output,
the adder after that to the right adds 6 to the nibble if the carry output is 1.
and the same thing for the upper nibble except the carry in is from the lower nibble adder and not the carry flag. the carry output goes to the carry flag like normal.

so, how i understand your equation: following that i get this: looking at the top left, the right black wire is A, the one to the left of it is B, and the black one in the top right is s.

but what if the changes don't really effect backwards compatibility with existing 65C02 code?

what i'm getting at is new instructions... again.
just this time they will be less... extreme...
so no multiply or extra registers or anything like that...

i have a few in mind that i can somewhat easily add that i would like some feedback on.
because it takes a real programmer to judge the usefulness of instructions.

SXY - Swap X and Y
same as before, simply swaps the contents of the X and Y Register

ICC and DCC - Increment with Carry, Decrement with Carry (or borrow?)
these are a bit more interesting. they take a byte from Memory, add/subtract the carry to/from it, and store it back into Memory.
they can use the same logic as ADC and SBC, only differences being that instead of "A + M + C -> A" it would be "0 + C + M -> M"
this means that unlike other Increment and Decrement instructions these would also set/clear the Carry flag, allowing you to inc/dec multibyte values in Memory without having to modify the Accumulator.
another interesting side effect is that these would work in Decimal mode... allowing you to inc/dec multibyte BCD Numbers...
it takes like 2 less bytes than a regular 16 bit inc/dec function but therefore works with BCD and can also easily scale to 24, 32, etc bit numbers without even more branches.
as for addresing modes, i thought about these: Absolute, Absolute X-Indexed, and Zeropage.

SEV - Set Overflow flag
because why not?

and lastly, this is more of a joke, though it would be easy to implement
you all know the different indirect addressing modes for LDA/STA... but you know which one is missing? D O U B L E
I N D E X I N G !

.

but besides that i'll still be finishing the "pure" 65c02 Verilog code like i originally said
but i might also add this other version of it with the additional instructions.

anyways, as always tahnks for all the help i get on here. without this forum i would've never gotten this far into a single existing CPU....

You can do some of that kind of thing with self-modifying code.

Nothing funny about this -- there's a perfectly valid use case, as when X indicates the location in zero page of a pointer to a multi-byte object --even an object as simple as a 16-bit word. (LABEL,X) will only get you the first byte; subsequent bytes require post-indirection indexing. (Or self-modifying code, as Garth says!)

Forth is one scenario where it's entirely commonplace for X to indicate the location of a pointer to a multi-byte object. That's because Forth commonly uses X as a stack pointer, and it's routine for an address to appear on stack.

My KK Computer from 1988 extends the 'C02 instruction set, and some of the enhancements pertain to Forth. Of these, the most notable is the 9-cycle ITC NEXT instruction. But KK also includes a form of (LABEL,X),Y addressing. For details, see X-Indirect-Y Addressing Using the W Register.

-- Jeff

yea but that's a bit cheating as you can do basically anything with SMC.
neat, so it might actually be useful.

i also thought about adding 16 bit relative branches and JSR Instruction(s).
but then i remembered the 65CE02 already adds those...
so i think i'll do the same thing as last time and push my own version back again... and forcus on getting an already existing CPU working.
welp, now i set my mind on it. so RIP adding new instructions until i got the 65CE02 working.

i'm always so uncertain with my goals... dammit.