65Org16 Assembler on custom Xilinx Spartan 6 FPGA Hardware

[ElEctric_EyE]

After doing the schematic for the JTAG section, I found a glaring mistake. The voltage pin on the JTAG connector, K4, is connected to 3.3V. According to figure 2-12 in UG380 it should be connected to VCCAUX which in my case that's 2.5V.
It's all CMOS, it might still work. I'll have to try it out before any modifications.

Anyway, here's my schematic of the daisy chained SPI JTAG section what I have done on the layout for V1.1.

[BigEd]

I've a feeling that mistake will cause a JTAG programmer to use 3.3V levels - which might stress, or might damage, the JTAG inputs of the FPGA. It might be worth looking into. You could stack a connector adaptor board which substitutes the 2.5V level.

[GaBuZoMeu]

I second BigEds thoughts. 3.3V might stress or damage your JTAG port.
Perhaps you simply insert a small linear regulator like these. I have used them for customers who wishes to separate analogue and digital supplies out of one (noisy) SMPS supply. So far no issues known.

[ElEctric_EyE]

Well, there is another mistake. U19 and U20, the SPI Flash's, should be powered by 1.8V not 2.5V. Not sure what I was thinking. I know I was looking at more than one design from companies that post schematics for their boards, in addition to UG380. My JTAG setup is non-standard and not clearly presented in the Configuration Guide. I maybe should have utilized the Xilinx forums...

At this point I'm seriously thinking the first run of boards I won't do any soldering. It will be mainly to ensure proper parts spacing and clearance, and power supply routing. I jumped the gun.

EDIT: Wow, serious problem with powering the FPGA SPI Flash's with 2.5V. Max VCC is 1.95V. Design error crept in somewhere... Feeling more confident now!

[ElEctric_EyE]

So progress continues on V1.2. I've added a 'more correct' JTAG interface schematic to the head post. Working on the power supply section schematic.

Here's my updates so far on V1.2:

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2.12.2019
Moved S2 silkscreen to proper position.
Slave Program and Master Program are in Bold text top layer silkscreen.
Moved K6 silkscreen to better position.
Added C130, C131 to top silkscreen.

2.16.2019
Power to JTAG connecter changed to 2.5V from 3.3V
Power to FPGA SPI Flash's changed from 2.5V to 1.8V
VCCAUX power vein changed from .025 thickness to .040
VCCAUX power vein to individual pin connection widened to .025 from .010
VCCINT power vein to individual pin connection widened to .025 from .010

[ElEctric_EyE]

Feeling more confident on the JTAG section. I started a thread on Xilinx a few days ago and a Xilinx employee there was very helpful and patient.

The V1.1 boards have been made and shipped. I should get them by 2/26.

[ElEctric_EyE]

Anxiously awaiting the boards today. Will have pics later...

Been working on V1.2. Alot of progress has been made.
Most notable is the 5V trace on the bottom layer has been shortened considerably by doing some work in widening the separation between the Master S6 and the 2 bottom SyncRAMs.
Also, I was able to stuff in another SPDIF optical output. The first SPDIF output is just for pass thru, this one is for outputting modified digital audio. After discovering that the Spartan 6 has the ability to have an SPDIF transceiver in the Core generator, I had to add this output connector.
Lastly, I rearranged the order of TDI & TDO between the S6's & JTAG so the Master is the Master in ISE14.7 and the Slave is the Slave device, i.e. the last one in the chain is recognized as the Master.

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2.12.2019
Moved S2 silkscreen to proper position.
Slave Program and Master Program are in Bold text top layer silkscreen.
Moved K6 silkscreen to better position.
Added C130, C131 to top silkscreen.

2.16.2019
Power to JTAG connecter changed to 2.5V from 3.3V
Power to FPGA SPI Flash's changed from 2.5V to 1.8V
VCCAUX power vein changed from .025 thickness to .040
VCCAUX power vein to individual pin connection widened to .025 from .010
VCCINT power vein to individual pin connection widened to .025 from .010

2.18.2019
Added K9 SPDIF out connector to the top of the board.
Widened all spare I/O vias from Slave S6/U21/K9 to .014/.031 vias to accomodate wire wrap wire.

2.22.2019
Lowered U4, U6, U16 and extended I/O lines from U2 to U4/U6 in order to route a shorter 5V on the bottom layer.

2.26.2019
Added C132 to K9 on bottom silkscreen.
Switched TDO/TDI on U2 & U3 so Master Spartan 6 is Master in ISE14.7 and Slave is Slave.
Tightened FPGA JTAG connections.

[ElEctric_EyE]

Got the V1.1 boards in! VGA connector from the PVB project footprint fits right in, just for size comparison. This is a 2.5"x4.5" power packed board. Checking all I/O connectors now.

[ElEctric_EyE]

VGA, 5V 11Amp Power receptacle and microSD card connector layout look good.
However, right above the VGA connector solder mask is covering up the videoDAC heat sink connection. That green square in the middle.

[BigDumbDinosaur]

ElEctric_EyE wrote:

VGA, 5V 11Amp Power receptacle and microSD card connector layout look good.
However, right above the VGA connector solder mask is covering up the videoDAC heat sink connection. That green square in the middle.

How do you plan to solder those fine-pitch components?

[ElEctric_EyE]

For the smallest components I use a medical grade needle with liquid solder and hot air with controllable fan speed. Also a pair of fine tweezers to place the parts. I have a hot plate too, but I don't think I'll be using that because the board is being assembled in stages.

[ElEctric_EyE]

V1.2 Production run is under way! All IC's and connectors have been placed and footprint mod's been made.
I have a new 43" monitor, hence the larger pics. Enjoy!

[ElEctric_EyE]

Got the boards in, soldered just the VRegs and power connector and started looking for shorts with the ohm meter before powering up and measuring voltages. Found one short between the 3.3V vein to GND. That does it for this board! The short is on the 3rd layer. It was a modification I made to the vein thickness and overlooked that it was touching a via pad. It was one of the latest modifications, so I'm still confident and proceeding with V1.3. Will be a few weeks before I post. I guess if I was an employed board designer I might be fired right about now.

[GARTHWILSON]

So you know exactly where it is? Can you drill through in just the right place to sever the short, without damaging other things?

[Dr Jefyll]

Yes, drill or use a Dremel tool... ??