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ElEctric_EyE
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PostPosted: Wed May 25, 2011 1:10 pm 
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I need to pay more attention to the code. Was rushing...
I think this is correct now. Will test...

HOORAY, It is running!! :D

Code:
 *= $FFFFE000                 ;START   COPY PATTERN $AA55
                              ;FROM $10000000 TO $FFFEFFFF (($FFFE X 10000) + FFFF)
                              ;
FFFFE000   LDA #$0000         ;00A9 0000
FFFFE002   STA $0000          ;0085 0000
FFFFE004   LDA #$1000         ;00A9 1000
FFFFE006   STA $0001          ;0085 0001
FFFFE008   LDX #$FFFE         ;00A2 FFFE
FFFFE00A   LDY #$0000         ;00A0 0000
FFFFE00C   LDA #$AA55         ;00A9 AA55
FFFFE00E   STA ($0000),Y      ;0091 0000
FFFFE010   INY                ;00C8
FFFFE011   BNE FFFFE00E       ;00D0 FFFB
FFFFE013   INC $0001          ;00E6 0001
FFFFE014   DEX                ;00CA
FFFFE015   BNE FFFFE00E       ;00D0 FFF6
FFFFE017   JMP FFFFE017       ;004C E017 FFFF


EDIT 5/28/11: Fixed the LSB on the JMP vector
EDIT 5/27/11: Fixed $FFFFE005 from $0000 to $1000
EDIT 5/25/11: 1 final correction to the bne offsets


Last edited by ElEctric_EyE on Sun May 29, 2011 12:58 am, edited 3 times in total.

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Arlet
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PostPosted: Wed May 25, 2011 1:31 pm 
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ElEctric_EyE wrote:
BTW so far, I am seeing a (CLK to setup) of 16.8ns. I was hoping for more, but this is still with the defunct BCD mode intact. I will try to trim it out as well, before posting to github.


What ISE version are you using ? It looks like the newer versions (12.4 or 13.1) are faster than the older ones. You can also play with the options: right click on 'Synthesize - XST' and pick "Process Properties..." You can change Optimization Goal to "Speed", and Effort to "High", and see if you get better results.

If your slowest path (check timing analyzer) involves the 'Z' flag out of the ALU, there is a small improvement we can make:

Right now, the Z flag is registered inside the ALU, which means that there's is 16-input NOR in the (long) ALU path. Instead of doing that, we can calculate the Z flag inside the cpu.v module, which moves this 16-input NOR to the Z flag update path, which isn't nearly as long.

Code:
    //     .Z(AZ),

and instead put this somewhere:
Code:
assign AZ = ~|ADD;


Last edited by Arlet on Wed May 25, 2011 2:38 pm, edited 1 time in total.

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ElEctric_EyE
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PostPosted: Wed May 25, 2011 2:12 pm 
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Arlet wrote:
...What ISE version are you using ? It looks like the newer versions (12.4 or 13.1) are faster than the older ones. You can also play with the options: right click on 'Synthesize - XST' and pick "Process Properties..." You can change Optimization Goal to "Speed", and Effort to "High", and see if you get better results...
[/code]


Using 12.4 right now. I think I've tried that at one point and it didn't seem to make a difference. I'll try it again though, now that everything is working in simulation.

Arlet wrote:
...If your slowest path (check timing analyzer) involves the 'Z' flag out of the ALU, there is a small improvement we can make:

Right now, the Z flag is registered inside the ALU, which means that there's is 16-input NOR in the (long) ALU path. Instead of doing that, we can calculate the Z flag inside the cpu.v module, which moves this 16-input NOR to the Z flag update path, which isn't nearly as long.

Code:
    //     .Z(AZ),

and instead put this somewhere:
Code:
assign ZA = ~|ADD;


The slowest path right now appears to be the A0 pin @18.1ns. I'll try your suggestions.
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ElEctric_EyE
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PostPosted: Wed May 25, 2011 2:33 pm 
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Adding the last modification lowered O2 clock to setup down to 13.9ns from 16.8ns. And the slowest pin is now A2 @18.3ns.

You did mean
Code:
assign ZA = ~|ADD

and not?
Code:
assign AZ = ~|ADD
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Arlet
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PostPosted: Wed May 25, 2011 2:38 pm 
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Yes, sorry, AZ not, ZA.

Can you post the whole path for A2 ?
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ElEctric_EyE
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PostPosted: Wed May 25, 2011 2:53 pm 
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OK, corrected that. Now seeing clock to setup delay on O2IN @13.0ns. And slowest pin is A1 at 18.0ns.

How would I find the whole path of A1?
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Arlet
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PostPosted: Wed May 25, 2011 3:01 pm 
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ElEctric_EyE wrote:
How would I find the whole path of A1?


Select Tools->Timing Analyzer->Post-Place-and-Route...

It will show you all the failing paths (make sure you constraint is small enough that something fails). It should look something like this:

Code:
 Maximum Data Path: cpu/ir_2_1 to cpu/alu_out_12
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     SLICE_X33Y24.XQ      Tcko                  0.720   cpu/ir_21
                                                        cpu/ir_2_1
     SLICE_X32Y20.G3      net (fanout=6)        2.109   cpu/ir_21
     SLICE_X32Y20.Y       Tilo                  0.608   cpu/src<5>
                                                        cpu/Mram_regfile6.SLICEM_G
     SLICE_X32Y26.G4      net (fanout=5)        1.579   cpu/dst<5>
     SLICE_X32Y26.Y       Tilo                  0.608   cpu/alu_out_or000323
                                                        cpu/alu_out_or000314
     SLICE_X33Y26.F1      net (fanout=3)        0.232   cpu/alu_out_or000314
     SLICE_X33Y26.X       Tilo                  0.551   cpu/alu_out_or0003
                                                        cpu/alu_out_or000323
     SLICE_X37Y29.G3      net (fanout=16)       1.309   cpu/alu_out_or0003
     SLICE_X37Y29.Y       Tilo                  0.551   cpu/alu_out_shift0001<13>
                                                        cpu/alu_out_shift0001<12>1
     SLICE_X34Y28.F1      net (fanout=1)        1.102   cpu/alu_out_shift0001<12>
     SLICE_X34Y28.X       Tif5x                 0.968   cpu/mux3_6_f5
                                                        cpu/mux3_7
                                                        cpu/mux3_6_f5
     SLICE_X34Y33.F1      net (fanout=1)        0.580   cpu/mux3_6_f5
     SLICE_X34Y33.CLK     Tfck                  1.050   cpu/alu_out<12>
                                                        cpu/mux3_2_f5_G
                                                        cpu/mux3_2_f5
                                                        cpu/alu_out_12
     -------------------------------------------------  ---------------------------
     Total                                     11.967ns (5.056ns logic, 6.911ns route)
                                                        (42.2% logic, 57.8% route)


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ElEctric_EyE
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PostPosted: Wed May 25, 2011 3:36 pm 
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Interesting, I set up a top level constraint for the O2IN clock at 12ns, and it passed! Now it says best achievable case is 11.68ns. Will try 11ns next...
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ElEctric_EyE
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PostPosted: Wed May 25, 2011 4:01 pm 
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Is this something to be concerned about? Been giving me the warning since making the adjustment to the Z flag.
Code:
WARNING:Xst:2677 - Node <XLXI_1/_ALU/Z> of sequential type is unconnected in block <top_level>.




It did fail @11ns. You mean this?

Image
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Arlet
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PostPosted: Wed May 25, 2011 4:14 pm 
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If you click on the paths, you get more detailed information.

But 12 ns is pretty good. With the 18 ns, I thought something may be wrong, but 12 ns is fine. That's going to be pretty much impossible to improve.

And, yeah, in order to see the top speed, you'll have to play with the constraints. If you put the constraint at 20 ns, and the tools reach 19.9, they're not going to try any harder, so you'll never see the top speed.
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ElEctric_EyE
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PostPosted: Wed May 25, 2011 4:33 pm 
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Is this something to be concerned about? Been giving me the warning since making the adjustment to the Z flag.
Code:
WARNING:Xst:2677 - Node <XLXI_1/_ALU/Z> of sequential type is unconnected in block <top_level>.

__________________________________________________________________________________________________________________________


Also interesting to note, when I set optimize for speed to high. Max delay is 12.002ns. When I set it back to normal, it passes again with Max delay of 11.551ns...

Next on the agenda is to trim BCD out, which lucky for me I have your original .cpu and .ALU files from 10/27/2010 to compare against. But there are a couple places where I'm not sure whether I should trim them out of not and would appreciate your help.
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Arlet
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PostPosted: Wed May 25, 2011 4:39 pm 
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The warning is about the unconnected 'Z' output in the ALU. It's no problem, but
you can get rid of it by editing ALU.v to remove all references to 'Z'.
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ElEctric_EyE
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PostPosted: Wed May 25, 2011 5:57 pm 
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I think I've got the ALU.v trimmed of BCD.
Looking at cpu.v right around line 543 that contains:
Code:
AXYS[regsel] <= (state == JSR0) ? DIMUX : { ADD[dw-1:4] + ADJH, ADD[3:0] + ADJL };


Should I change it back to:
Code:
AXYS[regsel] <= ADD;
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Arlet
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PostPosted: Wed May 25, 2011 5:59 pm 
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No, it should be:

Code:
AXYS[regsel] <= (state == JSR0) ? DIMUX : ADD;


That's needed for the RDY support.
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ElEctric_EyE
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PostPosted: Wed May 25, 2011 6:11 pm 
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OK, excellent, I think i got it!
A few more changes to the comments and I'll post them on github!

Will let you guys know when I'm done :D
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