No, I saw the poopie brown truck deliver the box. I intentionally did not open the door to greet the man, because I had nothing good to say. It was already 2 days late at that point and I knew he was just a cog in the machine. Then I saw the box after he left... I was livid. I was taking pictures, intending them as proof if I needed it. So I figured I would post one, sorry for all the expletives (which you don't currently see, heh). I had posted before I opened the box as I had expected damage, but there was none. I told my wife if she wants to pursue it, then she can get the refund. She had already called them and they agreed a refund was due because of the delay alone. As for me, that was the LAST time I use them, all I care about is my CPLD started board... I am at the bottom of that STEEP learning curve I have read about concerning CPLDs, but I have all the tools necessary to learn, so I'm divin' in.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Looks like Elmer the Elephant sat on it. Geesh!

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Way back when (40 years ago, to be exact), I was involved with the Postal Service's ZMT (ZIP Mail Translator) project. I was at the Oakland California sorting center cranking code into the ZMT when I heard something that sounded a bit like a train wreck. I got up, looked around and saw a massive pileup on one of the package sorting machines. It wasn't pretty. Some of the cartons were busted open and their contents were being mangled by more packages piling up. I'm certain to this day that some lady's underwear went flying past me.

By the time the postal drones got the machine stopped there had to be about 50 cartons in various states of disembowlment. I suppose UPS runs into that now and then.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

After a week of messing with the software, this morning I was finally able to implement the logic into the CPLD. No need to learn verilog, thank God. You can input schematics and the software does all the work to generate the files, including the all imprtant .JED file for programming. It is all extremely simple to learn. It took me so long because the first time I tried to compile the work, I thought it locked up, and I aborted the program, and unbeknownst to me it saved a schematic with bad instructions... I'll leave it at that, but I am extremely excited at all the prospects open now.

The glue logic is only using a small percentage the XC9572's pins and capabilities. Only 12% of the macrocells, 6% of the registers, and 45% of the pins... Now I can easily make the memory map more focused.

For sh*ts and giggles, the past (maybe) 15 minutes I designed a 16 bit preloadable binary counter with the 16 inputs latched, from 8 bits and a select, to save pins. I just picked 2 8 bit binary counters, 2 8 bit latches, and an inverter and wired it up. And BAM, it tells you all the pin assignments, top speeds, everything. For comparison, the counter used 48% of the macrocells, 46% of the registers, and 95% of the pins.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

The ISE 9.2 software isn't perfect, but I've found as long as you have a schematic to work from, you can start a new project and enter the schematic fresh, and there won't be any problems. I've run into issues where I'll start modifying a schematic, and when I try to implement it, it gives netlist errors. Probably my fault but still, I have no complaints, I can get it to go through error checking and create the .jed file successfully...

Just to update, I'll post the final schematics with: discrete logic, the CPLD version that replaces the discrete logic, and the one with the SRAM window. None of it has been wired and tested, except for the discrete logic. I have some parts on order to implement the CPLD, so it'll be a couple weeks before I wire the last schematic up.

Discrete logic (old design):



Using XC9572 CPLD to replace the discrete logic (old design):


Inside the XC9572 CPLD utilizing all but 2 pins (new design,compare to original): This new one utilizes 21% of macrocells, 13% of registers, & 92% of pins... At this point, I would like to maximize pin usage.

EDIT: Added a divide by 2 and 4 from the FastClk input so user can hardwire a select from onboard divider to SlowClk. Fixed _DE00DEFF latch signal from address decoding to 5 bit flip flop from active low to active high (DE00DEFF). (Utilizing 23% of macrocells, 16% of registers, & 98% of pins)


Updated schematic to control a 16K memory window into 512K, using the CPLD logic from the last pic. Different Icons/Pictures, and Fonts will go into this space (right now my character fonts are occupying 4K out of the 8K EEPROM, and I am quickly running out of programming space)... It will be copied into faster RAM just like the OS, so the whole system can run @10MHz. I had to slow down the clock speed from 6MHz to 3MHz, to do the EEPROM to SRAM copy, due to the slow (150ns) 512Kx8 EEPROM. I'll be wiring it up in a week or two... (I ordered 2 oscillators 10MHz and 14.31818MHz, so the 10MHz and 3MHz speeds are not exact speeds on the schematic)

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Today I made a baby step and hooked up my XC9572 to the JTAG port. Not being very familiar with JTAG, I decided to wire up power to the CPLD and the TCK,TDO,TDI,TMS, and GND to the connector without hooking up VDD (I wasn't sure if it was VDDin or VDD out). After connecting the VDD, the software recognized the CPLD, erased it and programmed it, WOOO! Evidently the cable has an interface onboard...

Looking back, and for those interested, you just need the cheapie parallel JTAG3 cable ($12 from Digilent: http://www.digilentinc.com/Products/Cat ... ,395&Cat=5 ) and the Xylinx ISE 9.2i software (you have to register it, it's worth it), to get started with CPLD's. I am noticing now Digilent has their own software called Adept ( http://www.digilentinc.com/Products/Cat ... ,66&Cat=12 )which looks to be free as well. I'm gonna test it out and report back...

Working with Xylinx CPLD's has been VERY rewarding so far. I understand now why so many discrete logic IC's are disappearing. But now so are some of the faster older (32-84 pin ) CPLD's in PLCC form, the newer Coolrunner CPLD's (100+pins) seem to be available only in VQF type packages. Good luck soldering those...

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

The software only recognizes their newer, more expensive USB cable, so I couldn't test it.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

What type of USB cable did you get? Even USB 1.0 cables are rated for 12Mbps over reasonable distances.

USB consists only of ground, +5V, and two data pins carrying balanced data. If nothing else, the peripheral should have dropped to 12Mbps if USB 2's speeds were too much for it.

The eval kit I got came a JTAG3 cable that uses the parallel port. I think it's only rated for 200K/sec. It only took about 5 sec's to program the CPLD though

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I think Digilent's Adept software expects particular hardware in the USB adapter - it's not just a cable, it's a JTAG adapter. I get the impression that Xilinx's USB adapters are expensive, and Digilent have defined a different method which allows them to offer a cheaper, but incompatible approach.

If you're using the Xilinx software to do the programming, you'll need a cheap parallel cable (which you have) or a Xilinx-compatible USB cable.

Or, here's Thomas Scheuermann's recipe for building your own using an AVR ucontroller.

Oh, sorry, I misread the post. I thought you had used a cheap USB cable to start with, and it wouldn't work without the more expensive USB cable.

It's much too early in the morning for me. Sorry.

There's some hardware in my parallel cable as well. It is made by Digilent as it has a label on the parallel port side of the cable. I've not looked inside the shrink wrap to see what's inside there,yet (it labels the JTAG pins). Maybe one day soon... But the cable does seem to be working with the Xylinx IC. Now I can't speak for Digilent's USB cables.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I looked into this: a parallel port cable only needs a few resistors, although it will probably contain some buffers too. A USB cable needs to implement a USB slave device, which is quite a complicated thing to do.

Beware: I also read that any ordinary USB-printer adaptor will probably not have the flexibility to drive a JTAG cable.

I have the four resistors and other connectors for the simplest cable but I haven't yet soldered anything up, and I'm a bit nervous of harming my CPLD or parallel port if I get it wrong.

Here's a link from the Xilinx website for the parallel cable III schematic.

http://www.xilinx.com/itp/2_1i/data/com ... /fig13.htm

The buffers help protect the PC parallel port. Mine is based on this schematic and works great.


Daryl

This is the recipe I'm thinking of. Easier, cheaper, but perhaps less reliable and perhaps less safe.