it seems pretty useful for where the target device cannot take parallel communications.
I think trying to directly do serial communication from the cpu would be a pretty weird use of a pin.
the 6522 seems to be especially suited for handling this and other tasks, that is the 6522 seems like its a lot more than just a parallel to serial converter.

so far, no one has brought forth any real replacement for the 6521/6522. It is shown you can run a 65xx without one for specific tasks.
I will do some searches on digikey and mouser for ICs that use those same x86 or 6500 'modes' or protocols for control, as some of them may also function by directly interfacing with the 65xx, as was mentioned for the 'good DUART' thats not around anymore and the alternatives that have been stated to work without a 6522. I am slowly compiling a short list of 3-4 common chips, DUARTS etc that are used with or without the 6522, more without.

Id also like to break down the protocols/types of devices that each of the Chips can perform well.
I am aiming to get a list or chart that says "I one is trying to do X or Y, then options Q or M are good and J is ill advised."

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I have about 6 pcb designs and 3 prototypes with 6502 and/or 65816, none of them use 6522/6521. Most of designs use CPLD instead. Some designs are capable of video/ keyboard and work with CP/M like operating system, so they are not trivial designs. W65c22 plus W65c02 is $20 in small quantity. Commercial products are extremely cost sensitive.
Bill

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Ah, Bisync... haven't heard that term in ages. When I was in the field ('77 - '84) I had a handful of customers that used Bisync and SDLC. These were usually on leased line end points provided by Ma Bell. Bisync was used with 3270 terminals at remote locations for either 360 mainframes or System/3 Mod 15 midrange systems. Pretty sure all of my SDLC customers were on System/34 or System/38 machines connecting two sites with secure dedicated communications... kinda like a VPN between two networks, albeit 4800 - 9600 baud rates. I also had a couple customers that were using dial-up RS-232 on conditioned lines from Ma Bell... oh, the good 'ole days.

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Regards, KM
https://github.com/floobydust

This is an excellent post, I am going to copy this to the first page!
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absolutely.
one of the guys in my old lab was William V. Stoecker, he has been using computer vision to identify skin cancer for over 30 years.
back in the "Top Gun" days, he used the same tech to spot melanomas.
We were using computer vision for everything from skin to pancreatic cancer.

The more I have learned in the years I have been to college, it is how little I really know.


so I totally get what you mean, and I will be making a thread for that. this is a reference thread that goes over the basics for myself and other people that search for those terms. The reserved second post is for the MAX3100, the 16550 and why people dont like it, a few other chips like that the Intel PIC looks interesting, and a section on mcu for these tasks. Ill be updating the posts over time as I learn new information.

I absolutely agree with what you are saying about a specific project and application; this however, is homework.


very interested in the RS-4xx serial stuff. Ill be reading more later.

Could I ask, what can the 6551 do that a common UART cannot or vice-versa?
Any other good parallel protocol chips to review for starters?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

agree on the 6551, it seems like GARTHWILSON has a lot of use for them and knows their nuances. I would say, for specific 65xx things and integration they appear to be good on the surface, I am more interested in other chips myself.

Parallel protocols like the x86/8080 and 6800 control stuff for the chips like intel 8259/a, the national semiconductor USBN9603/USBN9604, and several others such as the Sitronix ST7528 lcd driver.
From the TL28L92 data sheet


those, I think, you can drive a lot of those from the 65xx with "bit banging" as direct connections. Like you could that DUART or the 6522, you do not need an intermediary controller/adapter/etc. a 65xx rather needs an I/O chip if you want to do much with it I think. Some chips bridge or implement a protocol or system.

I am looking at identifying those chips and functions that can go closest to the 65xx, to act as the, or one of the, primary I/O chips up to and including replacing the 6522. several duart chips exist, an interrupt priority queue and an lcd controller. Maybe a USB or such, or a variety of mcu. not a lot of things 'take the place of' the 6522.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

FWIW, in recent discussions about an SBC design we looked into the question of available UARTs, and I have some notes (by @hoglet) from that time, shared with permission:


For me, one important point is the discovery that some modern UARTs also have timers and GPIO, which means the UART can also serve as a VIA: one peripheral chip instead of two. And we also thought a dual UART (DUART) could be useful if one channel is for user access and the other for debug, or for a serial-connected subsystem such as storage, or display.

Although the project in question is for a 6809 system, everything applies to 6502 equally well.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Note, though, the 6522 can provide hardware support over just bit banging.

(1) First, you can bit bang the output and use the serial shift register for input by connecting MISO to CB2 and SCLK to CB1 and putting the serial shift register into operation mode 011 (bits 2 through 4 in Auxilliary and Shift register control at VIA+$0A). The shift register mode 011 shifts after the rising edge on CB1, so that is for Mode0 or Mode 3 ... you would need to invert the SCLK line to do this with Mode1 or Mode2.

(2) Second, with the 65C02, you can use the write hardware handshaking pulse mode, mode 101 in CA2 control, bits 1-3 in PCR at VIA+$0C (in Port A, since the pulse mode uses either CA2 or CB2, and the serial shift register uses CB2), to generate a Mode3 SCLK pulse on CA2. Wire PA7 to MOSI, write the data into Port A, then do a series of seven "ROL PORTA" operations to pulse the SCLK line eight times. The 65C02 "Read-Modify-Write" operations appear on the bus as Read-Read-Write, so with only one Write cycle, the ROR operation and the 6522 pulse mode work together correctly. (IIRC, the NMOS6522 does a write on the bus during the modify phase, and if that is correct, then an NMOS 6502 would requite "LDA PORTA : ROL : STA PORTA").

Mode 0 can be done with a two-input AND gate, with inputs from CA2 and one of the PB lines as an output GPIO and CA2. Putting 0 in the GPIO before selecting the Mode 0 device pulls the clock line low. Then the data is written to the output port, and then the GPIO is set high, which raises the SCLK line, followed by the series of seven "ROL PORTA" operations.

This leaves 7 GPIO on the VIA PortB, for SPI selects, or 5 if two are reserved for a bit-banged two-wire interface.

Also note that if you have a faster board, the 6522 pulse mode has a pulse of a single clock cycle, so if you have an 8MHz board, the pulse will require an SPI device that can accept a 4MHz or faster SCLK.

Also note that with a 4 gate, 2 input NAND, you can use this to generate all four Mode serial clocks lines side by side, making mode selection a matter of which SCLK line you connect to which device. Connect CA2 and CB1 directly together, so that internally your MOSI and MISO registers are running in Mode3. Use one NAND gate with a PBn output to generate an inverted Mode 0 serial clock, which is SCLK_Mode2. Use the second Nand gate as an inverter to generate SCLK_Mode3, and use the third Nand gate as an inverter to convert the baseline Mode3 input into Mode1.

I'm surprised that worked. I would have thought "ROL PORTA" would send three clock pulses - one for each read cycle and one for the write cycle - and mess everything up. When I've done this in the past I've taken care to only perform one operation per bit.

In the write handshake mode, the 6522 pulses the data available pin on every write. It ignores reads. But that did not give a single pulse on ROL in the NMOS 6502 and family (like the NMOS 6510 in the C64), since the "modify" in a "read-write-modify" operation was a write ... but the 65C02 changed that to a read on the modify.

But do note that it is not a "wire-only" system ... as noted above, you need a clocked d-latch (eg, one gate on a 74x74) to lag the pulse from CA2 to CB1 by a half phase, so that CB1 is pulled down on the rising edge of PHI2 and pulled up on the following rising edge of PHI2, and since the datasheet notes that the data must be valid one full clock cycle after the rising edge of the CB1 external pulse, then you need a transparent d-latch that latches when a Mode0 or Mode3 SPI serial clock rises ... which means if the latch enable is active low as with the 74x75, you need to invert the SPI serial clock to get the d-latch enable. So half of two dual bit latches and an inverter.

And since this is a Mode3 system, to control a Mode0 SPI device you need to be able to hold the serial clock on the SPI bus low while the master serial clock is idle high. If you have a spare AND gate, you can dedicate a VIA GPIO to that task, fed into the AND with the internal serial clock, and the output taken as the SPI bus serial clock. For Mode0 operation, the GPIO is taken low before pulling the select low, then after the first bit is output, the GPIO is taken high. Then when the SPI output byte has been sent and input byte received, the GPIO is taken low again.

A handy way to do this is to store the Mode0 state with a TSB/TRB bit flag for the GPIO that controls the Mode0 phase shift. Then the state for Mode3 is to just store a #0 in the CPOL status location, and "LDA CPOL : TRB VIA_PORTB" will take the GPIO low if the appropriate bit is set in the CPOL byte, and just be an eight clock NOP if CPOL is zero.

It is handy if PB6 or PB7 is used for that phase shift bit, since then you can test if CPOL is set up for Mode3 with a BIT instruction and the S or V flag, and handle the first bit in a side routine if the SPI bus is working in Mode3.