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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

This is the Bank Address Latching Circuit from W65C816S datasheet that drogon mentioned:There isn't a dedicated IC to break it out but that's probably for the best. It would probably cost tens of dollars whereas a couple of 74 series ICs have probably cost me not much more than a dollar and I've just dropped them in and forgotten about them.

If you're using a clock oscillator running at twice your clock speed and running it through a 74x74 flip-flip to get a nice 50/50 duty cycle then you will already have the inverse clock from /Q and will not need the inverter. In my case I need a 74LVC4245* to do voltage translation as the '816 is the only IC I have that is at 5V CMOS voltage levels - everything else is 3.3V TTL voltage levels - so I needed a '245 anyway. That leaves only the '573 as a bit of a nuisance.

Adrien Kohlbecker speaks about the latching circuit in his first two videos Bank Address Latch and Data Buffering on the '816. He goes into quite a lot of depth in the timing requirements too.

* Actually I used a 74ALVC164245 because apparently I'm a masochist who likes soldering 48 pin 0.5mm pitched leads . It's a 16 bit voltage translator and I used the other 8 bits for up-translating the interrupt lines and PHI2 or something.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

So the shared data pins, they are clearly R/W depending on what they are doing at the time, and the rest of the data pins are R/W; what about the rest of the address pins?

I know its a silly notion, I just want to make sure, the address pins always assert a voltage, they always write, they never are selected or driven or use to read by the 65816/6502 correct?
you cannot use the CPU to read from address pins(except the shared pins when in data cycle), and what happens if say, you try?

Address pins are output only. There's nothing you can do to read from the CPU from them. You can't try.

I am greatly leaning towards following/implementing/using the ISA/PCMCIA/PCI/CF standards for busses.

ISA 8-bit pin maps to 6502 I think, ISA 16-bit and PCMCIA/PC-CARD/Cardbus to the 65816 I think.
Another way to look at these is 1 or 2 Ports of a 6522, etc. While the PCI is 32 bit and I am uncertain if it will function (that is any controllers for it) if run under 33MHz, there may be ways to offer a 32 bit bus.
PCMCIA and ISA are both suited to 6502 and 65816 devices at first look.

Any caveats implementing ISA in 8 bit for 6502 (and 6522 and a few others) and RAM, or a 16 bit ISA for a 65816 etc?

I am planning to make a schematic or diagram of a 6502 and an 8 bit ISA slot.
This is the AT Bus. I am also looking at Lee Davison's IDE work here, as that is basically AT on a cable.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

'265s starts at 32768 hz, looks for external routines to JMP to up to three times, and if not found, it continues executing internal ROM, that is able to detect several clock speeds so it can configure its internal serial port to a bps setting that can be in sync with standard bps speeds.

*BUT*

If an external routine is found, it JMP there and the programmer is free to disable all '265s internal stuff and keep the 65816 core, that can use the 16MB with no external chips at all.

With "by disabling the internal stuff" I mean that the hardware designer must provide all the chips needed to have a working computer, like any other 65xx computer would need.

Also, the fact that the '265s is rated 8mhz means, as previously said, that at WDC they tested it up to that clock speed, but it don't stop a hardware designer to try to clock it higher.

awesome, I might look into using the '256 for some stuff. I see the chips do not just come in a breakout-board they can be ordered as discrete ICs. having a few of those features available on-chip is not so bad... it just seems wasteful to have all this stuff and not be using it. I kinda, at some point, might consider using a bunch of 816s or 265s in a cluster setup, and the 16MB local to each chip can act as a cache. webpage even says it has a multiprocessor buss... I might look at that down the line

for a home bench, exceeding a datasheet spec is fine. overclocking is great for a user to do.

I am looking at commercial distribution on some projects and I would not send a product out that exceeds manufacturer's documentation, especially if I want a UL stamp on the board and some kind of insurance.

I am looking at a 'slow bus speed' of 6MHz, at half the 12Mhz clock a bunch of stuff wants. should be okay there. Having the d0-d7 and a16-a23 demultiplexed on board is fine, especially for solutions that use a Programmable Logic Chip, its not a lot of real estate either way. It may also lend itself to other logic chips for operating on a 32-bit bus, such as PCI

my thoughts on PCI are, since I have this alternate clock cycle with data/address pins I have to break out anyway, and if I had a 6522 on the board, it does not seem difficult to use the upper 8 address lines of the PCI buss to hold things like RAM or POM banks and other peripherals or signals from one of the nanks of the 6522 (or like a 8 bit register/latch thingy?)

Im starting 6502 on little ISA, 65816 on big ISA, and going to PCI/CF/PCMC/CardBus after that.
Im also curious about dual chips, say 65816/265 acting like a 32-bit cpu, and using 'full 32-biit PCI'.

I think 24-bit big ISA and PC/104 are probably good goals.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?