8 Pins, 26-33 on this pic I viewed here: https://encrypted-tbn0.gstatic.com/imag ... E&usqp=CAU

are D/B 0-7, shared or 'multiplexed'? pins that are both data and address pins.
this raises numerous ideas about the PC-MP/MC notion of video or other data over address pins instead of data pins.

for the moment however, I want to focus on the various circuits that break these pins out into two distinct paths, one for data and one for addressing. they are written in the datasheets. if it is that simple, is there an IC package with this already done, and if so, why not?

Yes, the upper 8 address bits are multiplexed with D0:7. The reference datasheet suggests a 2-chip solution. I get away with one, but you'll likely have some sort of CPLD on your device, so you use this instead.

-Gordon

_________________
--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

so there is no package bigger than 44 pins? no 64 pin with that already done? you must always implement a demuxing solution yourself for all 65816 chips?

no, I was going to avoid Programmable Logic Devices for the most part, beyond ROM code for each chip. I am more likely to include a socket for a memristor IC than an FPGA or CPLD.

That's right, and I'm surprised you don't know this already. The data sheets are freely available.

You may wish to look at the W65c265 though.

-Gordon

_________________
--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

I have looked through the sheets yes, more wishful thinking and hopefulness that maybe one was out of date or that no other fabricator had one available.

ok, so is there a good list of mux/demux circuitry options here on the board. as you mentioned there are options listed in the datasheet itself; you said you had a method with only one chip used? are there any other methods known for the data/address communication circuits?

Id like to understand this process a bit better, Ive read in a few places though Im not 100%.
on one half of the cycle the pins have an address on them, and on the next half of the cycle have the data for that address (or is getting it), and this switches back and forth on hi and low sides of the clock circuit?
or is this every other clock cycle?

I have been reading a lot of datasheets the last few days, Im almost ready to filter out which ones to read again. I've also been gathering books...

I'll keep reading the forums and documentation, any information on just this one aspect of the 65816 is really helpful.

As for the 65265, it does offer a basic 'core' of an mcu, however it would be superfluous to my current project. I am hoping my OS runs on it well.
The PIC Im using is going to do pretty much all the I/O beyond audio/video.
I still need to talk to it and RAM though

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

wayfarer, probably Gordon mentioned the '265 in response to your questions about demultiplexing.

The '265 is capable of directly outputting all 24 address lines, unlike the '816 which requires two external chips as shown in the datasheet. (In the right circumstances just an address latch alone may be sufficient, but there are some very sound reasons why the datasheet recommends a transceiver as well.)

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I get you, it is not a bad chip, its just locked at 8MHz and not what I need right now.
Is there any interest in a 65816 in a 64-pin package that is already demuxed that does not have all of the features and limitations of the 65265?

why locked at 8MHz?
the 65C02/816 aren't "locked" to 14MHz either, that's just the speed WDC guarantees every chip will be able to reach. even my own C02/816 SBCs ran fine at ~20MHz.
so i'm pretty confident the '265 can get beyond it's rated 8MHz.
i did actually buy one of the 4 chips mouser had in stock because i was interested in it's functions. but so far i haven't done any work on a PCB to try it out.
of course once i start that project i'll post about it on here, since there overall seems to be few projects, and therefore not a lot of info around the chip.

https://www.westerndesigncenter.com/wdc ... s-chip.php
https://www.westerndesigncenter.com/wdc ... s-chip.php


both of these mention 8MHz Bus speeds, and the datasheets only list 1MHz and 8MHz speeds, there does not seem to be a lot of indication of clocking to say 6Mhz or 3MHz. The '265 has a lot of extra stuff on it, that will not get used in my case, so I was looking for something in the middle, really, just a 65816 in a package with the busses laid out. We might see one, and other chips get revised to, I see datasheets and revisions around the WDC site in the last few years.

I may try to do something with the '265 or '134 when I start getting to the 3d printer stuff.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Possibly you mean this thread, Garth:
Index of threads for improved 6502 and derived architectures

Yes I went through a lot of that, seems that everyone has their own ideas about a 32-bit 65xx chip.
I have my own notions. Has anyone compiled the shared features of each proposal?

to me, backwards compatibility with the 6502 and 65816, using the same instruction set, etc are pretty crucial.
a 32-bit 65816, or 65xx32 or such should be an extension of the 6502 nd 65816 instruction addressing and thought process.
to extend the ASM, I would focus on math functions and possibly return to analog computing.
some interfaces to memristors and the circuitry for statistics, calculus, algebra on a 32-bit 65xx, and the database comparator code, Ill need to study the 65xx ASM to say more... whats this about a Random Execution Engine, in the 65xx core? they just throw hex math at it from two directions and it crosses in the middle and comes out processing? Id look at some of these things, it seems like you have two planes:
one plane has the operand and data, the other plane has the address mode and operand or data, and they cross in the middle and the cells that light up get collated into bits on the other end, literally passing electric charges in a matrix through each other.
Id extend the bitwidth, keep that intact, and work on any new address modes that emerged and try to get some more math in there.

These would extend to 64-bit, though Im not certain it is really needed for most MCU, MPU work, the dsp, the DAC/ADC, the special circuits and registers can do these things. 32-bit offers enough increase in RAM and storage, it would hold the 65xx brand another 15-30 years, as it is already likely to do. building on the work in the 65265 in what looks like better multiprocessor functions (its what it says), might lead to that 32bit function.

beyond this, I would instead prepare for the big data crunch with 128-bit registers and a 256-bit or bigger accumulator. this is for searching and referencing huge archives and databases with thousands of dimensions across millions of records. big data. calculus performed on statistics and vice versa. offering chips in that range that worked on 65xx ASM would be really cool. if a few years ago we were at 2^73 or so, having 2^128th power in the near future, that worked on the 65xx 'language' would open a lot of doors, telco, power distribution, big data, machine learning.