Thanks - I think I get it now. I kept thinking by mistake that 74x138 outputs float when inactive.



Those are some cool articles, thanks! I can't believe they are actually from 1980!

In the meantime, I've added some plumbing for "mystery" (c) pins and replaced 6502 with 65c02s. Next on my agenda - clock!

EDIT: Considering I'm going to run @ 1MHz, can I simply tie /CE & /OE of EPROM together (as in my schematic)? If I understand correctly, I need to separate them and wire /RD->/OE + ROM/EN->/CE only in case I want to run on higher frequency and make EPROM reads faster, correct? Or do I still need to separate them in my scenario?

_________________
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD

Oops, sorry, I over-reacted! I thought you were treading a certain path and I was wrong about that. As noted elsewhere, a simple push button and pull up is enough for many purposes. See here for example. A reset controller is preferred by some but is certainly not always necessary.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Needless to say, the whole story around a proper reset circuit has been beaten to death. Several folks out here have shared or linked various methods. Bottom line, there are many ways to generate a reset. I would suggest they fall into a few categories:
- proper engineering: (call it best practices if you like) using the specifications in the data sheet and designing a circuit to meet those specifications.
- cheats: using a partial from above, meaning it's not quite the proper deal but will generally suffice most of the time.
- hacks: using a lego approach of extra gates/inverters and other components to get something that works.

In defense of the above, an example of each:
- proper engineering: Any of the old Commodore machines (VIC-20, C64) which used a 555 Timer and surrounding parts to generate a reset signal that feeds a 7406 open collector inverter driving the reset line.
- cheats: Grant's minimal designs along with countless others... but let's be honest, they don't work reliably all of the time.
- hacks: Look at the reset line for the Commodore 1581 diskette drive... a total hack of too many components.

For helping a newbie get started, I'll always take the proper engineering approach, but that's my view on the subject, which goes well beyond the reset line to the rest of the design. On the other side of this, presenting too many oddball circuits just confuses a newbie. When starting something new like a SBC project, there are enough pitfalls to fall into without giving them additional ones to pick from.

_________________
Regards, KM
https://github.com/floobydust

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks for the details! I was not aware of those differences in 74xx types. Also, I think you're right - I'll reserve space for I/O.
Your diagram has also been extremely helpful - it greatly helped me understand how NANDs can be combined to achieve awesome results!

(...1 hour later...)

Okay, so it's took me some effort to figure out the 74xx puzzle to make proper changes for including I/O in my memory map. I'm not sure if this is a good solution, but here's what I came up with. Let me know what you think!
BTW, for "reserved" I could invert A12 through one remaining NAND gate and drive a second 74x138, thus getting 16 I/O selectors. Not sure if I ever need that many!



I wonder if my schematic will work. Looks like it's all correct, but I'd appreciate an extra pair of eyes on it.

P. S. Today I learned that NAND is called a universal gate!

EDIT: I'm wondering if RAM's /WE should come from /WD or CPU's R/W? According to the primer, it should be R/W:
> The R/W line will also go to the RAM chips' WE pins.
...but what's the purpose of /WD then? I thought /WD should be the one driving /WE on RAM (since /WD is synchronized with Ф2).
EDIT 2: I wanted to avoid having accidental writes to ROM (which may result in shorted data bus). I've achieved this by passing inverted R/W into ROM's OE. Is this a normal way to have this kind of protection?
EDIT 3: I've made a simple interactive demo for myself to test it around: https://circuitverse.org/simulator/embe ... s-selector
EDIT 4: I think I've already found a use for "reserved" 4k segment: EEPROM! I'll use smth like AT28C64. Persistent segment in 6502 memory map - how cool is that?

_________________
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD

From 1980, the same as me! I was sad that that particular magazine and that column only ran for 3 issues.

I've been a little busy this week with work and didn't have time to post to this thread much; I wanted to say that I've really been enjoying it though! I like how every one of your schematics is better than the previous one. It seems like you are making very fast progress.



You *can* do a lot of things. You could, for example, just tie all of your CE\ lines low and juggle read and write signals to make sure that the RAM and ROM aren't fighting over the bus.

Garth's circuit and BDD's circuit don't work the same way, but both of them do work! Already at this early stage you're faced with decisions about what makes sense for *your* specific project. At the risk of overwhelming you with homework, it might be a good idea to consider *why* both BDD's and Garth's circuits work, in spite of their differences. Here's something that might help with that:

https://laughtonelectronics.com/Arcana/ ... iming.html

My current favorite memory interface is this one:

That diagram comes from an old post here, but for the life of me I can't track down the thread it was originally posted in. If memory serves, it was created by Jeff Laughton (forum member Dr. Jeffyl), who also made the timing diagrams above. My current board uses a variation of this idea and a 74AHC139. It's running at 12.6MHz!

Edit: Hahahahaaaa found it!

viewtopic.php?f=4&t=511&hilit=139&start=15

_________________
"The key is not to let the hardware sense any fear." - Radical Brad

That's quite a nifty little circuit. However it doesn't have any provision for I/O devices - you'll need at least one of those to get a usable system. You could fix that by connecting A14 to input A of the top decoder, then use Y3 to select ROM (addresses C000-FFFF) and Y2 to select I/O (8000-BFFF). Then you can also use A15 directly to select RAM instead of using one of the decoder outputs - that will give RAM between 0000 and 7FFF.

Using the 74139 for I/O decode and read/write with clk2 validation goes way back. I posted Doug Beattie's schematic (dates back to 2000) here:

viewtopic.php?f=4&t=6667&p=84821&hilit=diy6502a#p84821

Jeff converted it to black and white which is much easier to see.

Also, the Commodore 1581 diskette drive did much the same using a 74139, which dates back to 1987:



What's old is new

_________________
Regards, KM
https://github.com/floobydust

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks! I'm learning a lot of new cool stuff, and it's so exciting to be able to share it with someone!

I think I finally got the point of having /RD & /WD: it's there just to avoid bus contention at falling edges of Ф2. I had some false understanding of few things (specifically - when did reads/writes happen), but it makes so much sense now. Sometimes I have to wander for miles before I come back to the initial statement and am able to actually comprehend it. I appreciate your patience!



This is so cool, I haven't thought of feeding Ф2 into 74xx138! This seems to be very neat in cases when memory map needs to be easily rearrangeable.



Cool, I didn't know that. It's so nice that I can now look at real schematics of classic products and actually *understand* what's going on there. Takes one to know one!


This circuit was one of my main sources of inspiration that helped me build my addressing, thanks for sharing! NAND gates feel like they we born for this task. In my case the memory layout is simpler, so all I needed was only 2 NANDs & a 74xx138!

_________________
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD

True, but not by much. Max propagation delay for the AHC139 is about 9ns, which is one ns slower than AC00.

ETA: Not strictly on topic, but:In this case, what's old is old, as the linked thread is from 2004! (Or maybe what's new is old?) When I first started reading 6502.org about 3 years ago, that nearly 20 year old thread was one that really helped my understanding of Ø2 and memory read/write timing "click." So much so that I still had that diagram from it saved on my desktop! And here I am, 3 years later, sharing it with another new person who will hopefully benefit from it as much as I did. This is one of my favorite features of this forum.

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"The key is not to let the hardware sense any fear." - Radical Brad

I'm actually really impressed that this forum has been around for more than 20 years now (oldest post I could find is from Oct 28, 2002). This is a rare breed in a modern world of pseudo-social-networks like tiktok or facebook. I cherish the fact I found this place and that it's still alive!

Few updates:

- I've started prototyping my design on a breadboard (mostly for testing things around, since in the past I've had some really bad luck with parasitic capacitances, wobbly connections & shitty chinese jumpers). As soon as I get the desired layout & selection of components, I'm going to move everything to a perfboard for a functional prototype before going for the PCB.

- Primer suggests to use 74LS04 for oscillator specifically. I disregarded that and used my 74HC00 with a 3.072 MHz crystal I've had around. Needless to say, it didn't work. As soon as I replaced it with 74LS04, I could get the oscillation like a charm.

- I can't wait for my W65C02S from Mouser, but I feel like it's going to take forever: their processing is slow, and the mail has also been rather slow recently.

Here's a mess I've made out of my breadboard so far. My next stop is caps, RAM & the CPU itself. Might take a while before I have those parts on me...

_________________
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD

You could also use an Uno or a Nano as a temporary clock source;

Actually, I was just thinking how painful it will be to remove EPROM, since every time I want to update the code I'll need to re-flash it. Your suggestion of using one of those boards for clock actually gave me an idea to use Nano as a simulator for DIP-28 ROM! I think there *should* be enough pins (12 addr + 8 data + /CE & /RD interrupts) for the task. Also, I'm not sure if 16MHz will be enough for this, I'll see if I manage to write a code that will take less than 8 CPU cycles of Nano to read the data (and I have serious doubts about this). As a last resort, I can just underclock my W65C02S so that Nano has more time to assert the data line.

I have a whole lot of ESP-based boards (NodeMCU, etc), but there's not enough pins on them. Might consider ESP32 for this, though it feels like an overkill. But hey - as long as it works!

EDIT: Note to future self - "never put EPROMs in the middle of the board with too many jumpers around, you'll need to remove it pretty often..."

EDIT 2: OK, so atmega328p & ESP-32 are off the table: the former takes 11 cycles to jump into ISR (687.5ns, source: https://www.embeddedrelated.com/showthr ... 1437-1.php) and the latter takes astounding 500 (!) cycles fo this - i. e. ~2us (source: https://www.esp32.com/viewtopic.php?t=422)... And that's the time it takes them just to start executing ISR.

_________________
/Andrew

deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
nice65 - 6502 assembly linter | My parts, footprints & 3D models for KiCad/FreeCAD