BigDumbDinosaur wrote:
You need to work out how to create address space for I/O, even though you don’t intend to connect any I/O hardware in this first go (an intention that might change after you get the thing running). Doing so will give you an opportunity to work with a 74x138 decoder. This being your first build, I suggest you leave $C000-$CFFF open for that purpose. That reference circuit I put in my previous post does that.
Thanks for the details! I was not aware of those differences in 74xx types. Also, I think you're right - I'll reserve space for I/O.
Your diagram has also been extremely helpful - it greatly helped me understand how NANDs can be combined to achieve awesome results!
(...1 hour later...)
Okay, so it's took me some effort to figure out the 74xx puzzle to make proper changes for including I/O in my memory map. I'm not sure if this is a good solution, but here's what I came up with. Let me know what you think!
BTW, for "reserved" I could invert A12 through one remaining NAND gate and drive a second 74x138, thus getting 16 I/O selectors. Not sure if I ever need that many!
Code:
+-------+-----+-----------------------+
| RANGE | TYP | Notes |
+-------+-----+-----------------------+
| $0000 | | NAND(A14, A15) |
| ... | RAM | |
| $BFFF | 48k | |
+-------+-----+-----------------------+
| $C000 | | !RAM && !A12 && !A13 |
| ... | I/O | |
| $CFFF | 4k | |
+-------+-----+-----------------------+
| $D000 | | !RAM && A12 && !A13 |
| ... | n/a | reserved (EEPROM?) |
| $DFFF | 4k | |
+-------+-----+-----------------------+
| $E000 | | !RAM && A13 |
| ... | ROM | |
| $FFFF | 8k | |
+-------+-----+-----------------------+
I wonder if my schematic will work. Looks like it's all correct, but I'd appreciate an extra pair of eyes on it.
P. S. Today I learned that NAND is called a universal gate!
EDIT: I'm wondering if RAM's /WE should come from /WD or CPU's R/W? According to the primer, it should be R/W:
> The R/W line will also go to the RAM chips' WE pins.
...but what's the purpose of /WD then? I thought /WD should be the one driving /WE on RAM (since /WD is synchronized with Ф2).
EDIT 2: I wanted to avoid having accidental writes to ROM (which may result in shorted data bus). I've achieved this by passing inverted R/W into ROM's OE. Is this a normal way to have this kind of protection?
EDIT 3: I've made a simple interactive demo for myself to test it around:
https://circuitverse.org/simulator/embe ... s-selectorEDIT 4: I think I've already found a use for "reserved" 4k segment: EEPROM! I'll use smth like AT28C64. Persistent segment in 6502 memory map - how cool is that?
_________________
/Andrew
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