Wow, thank you for so many responses, I really appreciate this!
GARTHWILSON wrote:
Welcome.
You'll need a reset circuit. It's not optional. The 6502 primer has a chapter on it.
You'll also need some sort of clock-generation circuit. The 6502 primer covers that, too.
Sure - I've omitted the plumbing part for the sake of brevity. This is my first time using KiCad and I'm still getting used to it.
GARTHWILSON wrote:
The RAM will be active when this input is low, which is the opposite of how you have it.
Not sure if I'm following: all 74x138 outputs & SRAM /CE & /OE are active-low, aren't they? (So the decoder will only ever select one RAM or ROM at a time)
GARTHWILSON wrote:
You cannot join '138 outputs. They'll fight each other. In some cases, you can keep the '138 enabled all the time; but you'll want to make sure two things cannot be enabled at the same time, for example a VIA and a RAM trying to put data on the bus at the same time, as they'll fight each other.
Can the outputs of 74x138 be joined via diode OR gate to mitigate this?
GARTHWILSON wrote:
Obviously you'll have to have some kind of I/O, or the computer won't be any good for anything at all. Plan accordingly.
Definitely. But for now, I'm trying to avoid anything other than CPU/ROM/RAM & glue logic for now to keep it as simple as possible, and my IO will be an oscilloscope and a bunch of LEDs.
GARTHWILSON wrote:
I would encourage posting your schematics in black and white. We have a couple of forum members who are colorblind, and for one of them, the light-green lines may be just about invisible, and the green against yellow is problematic too. In B&W, everyone can read it.
BigDumbDinosaur wrote:
Before I go further, may I request you post your schematics in monochrome?
Of course, I didn't think of this. Thanks for pointing this out!
BigDumbDinosaur wrote:
You didn’t mention whether you are going to use an NMOS 6502 or a 65C02. The latter is highly recommended for a number of reasons, not the least of which is the 65C02 doesn’t have the hardware errata of the 6502. Also, the 65C02 has strong output drive that swings rail-to-rail, whereas the 6502 has weak fanout that works at TTL levels. The output characteristic difference can give you grief.
Yes - I'm going to use 65C02 as it's still being manufactured, I've already ordered few of them from Mouser.
BigDumbDinosaur wrote:
Both versions of the SID are also TTL devices, so that is something else to consider. Of the two, the 8580 will be the much better choice. The 6581 needs a 12 volt supply, runs hot, is easily damaged by ESD and doesn’t follow the written specs for the device as well as the 8580. The 8580 can get by with a 9 volt supply, has less THD in its output and is less ESD-sensitive.
Yes, 8580 is definitely more reliable. I have few from new old stock (tested them with my C64C), I'll probably play with them.
BigDumbDinosaur wrote:
Garth answered this, but I’ll add a bit more to it.
Most SRAMs are designed to interface to Intel x86-style buses, which means they have three control inputs of interest (aside from the address and data pins): /CS (chip select), /OE (output enable) and /WE (write enable). /CS is controlled by your address bus decoding logic and is driven low (asserted) when the device is selected for access. When asserted, /CS, also referred to as /CE (chip enable), brings the SRAM out of hibernation and causes it to set up an internal data path to the cell that is to be accessed.
As the SRAM’s internal setup process is relatively slow, I always recommend /CS be asserted as soon as the MPU drives a valid address onto A0-A15. The 65C02 does this during Ø2 low, which means /CS should not be qualified by the clock (Ø2), since you will be unnecessarily giving up some timing margin.
Once /CS has been asserted, /OE would be asserted during a read cycle. The SRAM will drive the data bus one setup time after /OE goes low—that setup time is typically shorter than the /CS setup time. The MPU will sample the data bus near the end of the Ø2 high phase and latch the data at the fall of the clock. Although not essential in a 65C02 system, good practice will not assert /OE until Ø2 goes high, a hedge against data bus contention in some applications.
If a write cycle, /WE must be asserted, but only after the rise of Ø2. Qualifying /WE with the clock prevents data corruption due the buses momentarily being unstable shortly after the fall of Ø2. If writing is enabled while Ø2 is low, there’s the chance that two different cells in the SRAM might be “touched†as the address bus settles. Needless to say, debugging something of that nature would difficult.
Below is a circuit that fully qualifies reads and writes, and is suitable for use with hardware that has an Intel or Zilog interface, e.g., a typical SRAM or other non-65xx output device.
This has been extremely informative & helpful, thank you!