Forum member Michael has often posted about his idea for a jumper-configurable memory map. For example:

http://forum.6502.org/download/file.php?id=9128&mode=view

This seems like a cool idea to me, but no one ever seems to take him up on it. I was thinking I might try it; that way if I decide I don't like my I/O in Zero Page, I can just relocate it with a couple of jumpers! However, Michael's moveable-IO-space window is always at least 1 page in size. Suppose I wanted the option of a smaller (128 byte) IO space. Wouldn't this get the job done?

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"The key is not to let the hardware sense any fear." - Radical Brad

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I would also second BDD's suggestion on using programmable logic, as it will simplify the overall design, eliminate 2 or more chips and give you a much more flexible solution that can be easily changed.

I'm using the ATF22V10 as a single glue logic on my C02 Pocket SBC. The configuration allows for clock qualified read and write signals, RAM and ROM chip selects and 5- I/O selects that are 32-bytes wide each. You can also get a 5V part with a 7ns rating, so they are quite fast.

Regarding memory maps... I've been using the same one for decades with the 6502 (now 65C02). I always put the I/O in page $FE. As the 65(C)02 requires some ROM type memory to kick it off at the hardware vectors, I can keep ROM and I/O in a very small upper memory range. This allows a larger contiguous RAM address which can be quite useful... but again, it all depends on what you're planning on doing with your system.

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Regards, KM
https://github.com/floobydust

Context is everything - I believe Michael's suggestions are not about GALs, they are about using 74 series logic. Whether one uses one technology or another is often a personal preference.

For example


Edit: Here's another previous post from Michael.

It would be great if we could address ourselves to Paganini's question:

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Would an on-line image converter or something similar be of any help to you, Sir?

Cheerful regards, Mike, K8LH (Michigan, USA)

I would like to see this amazing quantum glue logic that can be implemented with *zero or fewer* chips! Your kung fu must indeed be powerful. Maybe we can sell the chips generated by the "or fewer" version and make a profit. (Or maybe that's where all those sketchy Ali Express logic ICs already come from!)





I will have to think about this for a while to really get a grasp of how to do it, but I think it sounds amazingly cool.



Each Q input is pulled low through resistors, by default. You can use a jumper to short it either to VCC (to move the window around in address space), or to the corresponding P input address line so that P=Q will always be true for that line, effectively shrinking the width of the comparator. The notion is that you can double the size of the window each time you de-activate the next low-order bit.

I suppose you might be able to do interesting things by removing random upper address lines from the mix, but I can't visualize what would happen; I think it would start mirroring the window, wouldn't it?

Edit:



BTW, I did read that in the Primer, and I looked for them when I went "comparator shopping." HC and AHC don't seem to exist on Mouser / Digikey, and AC is listed as "obsolete, non stocked" on Digikey. I see now they have them in F and ALS. I am uncertain about mixing logic families.

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"The key is not to let the hardware sense any fear." - Radical Brad

Yes, Paganini, I think you're on the right lines. You're using Michael's scheme but squeezing in an extra bit of decode by using the enable input: you've called it Gbar, Michael called it OEbar, and elsewhere I see it as E (active low). It took me a little thinking to understand what Michael is doing with the size and address jumpers, but it did become clear. (It would be good if you could link to the post where he shared that attachment - I haven't been able to find it.)

The only caveat I would have is that I haven't checked the logic for whether everything is the right logic sense - it's easy to miss an inversion here or there.

Here you go Ed:

viewtopic.php?f=4&t=7347&start=15#p95827

(Sorry, took longer than I meant. I got sidetracked because I discovered more interesting old threads I hadn't previously read. )

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"The key is not to let the hardware sense any fear." - Radical Brad

Thanks! There is a great deal of accumulated experience in the back catalogue... the dusty old threads.

Unfortunately, that post doesn't really explain how the jumpers work. I was trying to come up with a relatively intuitive method to set size and address. Basically, you fill in jumpers across the {size} rows in each column from right to left to set the size of the block. So four jumpers across the {size} rows in the A8, A9, A10, and A11 columns would set the size to 4096 bytes. The remaining columns, A15 through A12, are used to set the block address which in this case can be $0XXX, $1XXX, $2XXX, $3XXX... $FXXX. A jumper placed across the {addr} rows in a particular column represents a '1' while the absence of a jumper represents a '0'.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I notice Michael's original does use 47k - it's Paganini's version which has 4k7. That's the sort of thing I didn't check at all!

Another perhaps simpler possibility if using Windows 10/11 is the "Color filters" system setting which can render the whole screen in greyscale and can be turned on/off with a shortcut key if so enabled: