Previous thread: 6520 dissection

First: sorry for going a bit offtopic.

Frank and me had dissected quite some NMOS chips, but nothing CMOS so far.

By the end of 2022, we wanted to know if we might be able to dissect CMOS.

But the only CMOS chip which Frank had on stock in polygonized form was the 5719,
so we decided to make a try, and we now have proof that we might be able to go for CMOS indeed.

5719 isn't a 6502 related chip, sorry that, please discuss the 5719 schematics in a different forum.
If you have spotted errors in my 5719 schematics, please send me a PM, and I'm trying to fix them.

This thread is our ticket for dissecting 65Cxx CMOS chips someday in the future.
To make sure we won't forget the basics for dissecting CMOS, we are parking them here.

It would be nice if we could keep the thread mainly about the characteristics of the silicon
in Commodore MOS\CSG CMOS gate arrays and such.

;---

This thread is mainly about the basics related to dissecting CMOS,
with a little bit of gate level dissection of the MOS 5719 GARY "as a payload"
(which does address decoding and bus control in the Commodore Amiga),
brought to you by Frank Wolf and ttlworks.

Low resolution 5719R4 picture.
//for a three times higher resolution picture, you need to negotiate with Frank.



Schematic of the chip "as it is",
omitting the PMOS FET switches in the 2:1 multiplexers for better readability:



End result of the dissection:



The complete set of schematics with all steps of the dissection as a ZIP:



So far for the offtopic part,
now for some "CMOS shenanigans".

The 5719 chip layout says (in the South West corner) that the mask was generated in 1986.

Rumors say, that MOS\CSG always had some little problems with the CMOS process.

We know, that Commodore had used a Ricoh RP5GH05 CMOS gate array in 1541C\1541-II floppy drives,
the chip was labeled 251828-03,
McMaster has a microscopic picture of the silicon.
;
A datasheet of the RP5GH05 can be found at Bitsavers:
Rico Electronic Devices Data Book 1988, PDF page 102.

The data book says, that the design process goes like this:
The customer just "tinkers with the logic equations" and "the Ricoh RP5GH standart cells library",
and after that Ricoh does the chip layout.



Other CMOS gate array vendors probably had a similar design flow.

But the 5719 chip layout shows a "MOS style" test pattern, and the output drivers in the 5719 don't look like Ricoh.
In fact, the 5719 output driver layout looks very similar to the output drivers we have seen
in the 65CE02 chip layout.

So we could assume that the 5719 and the 65CE02 were designed and manufactured by MOS\CSG "in house".

Nevertheless, it's an interesting question whether MOS\CSG had bought design libraries
from other CMOS gate array vendors or not for designing 5719 and 65CE02,
but getting hands on microscopic pictures of the gate arrays manufactured by a dozend of different vendors in the 80s
(more than 40 years ago) for taking a closer look at the output drivers seems to be close to impossible.

//Output drivers make a nice identifying feature:
//because they tend to be big, and because they tend to be located close to the outer edge of a chip.

Now for the 5719 input pads.

In NMOS, input protection breaks down to having a resistor on diffusion layer
between the pad and a NMOS FET which switches to GND in case of a negative signal voltage,
before said signal enters the first inverter.

In the CMOS 5719, the game is a bit more difficult.
Let's take a look at the KBRES# pad.

North from the pad, we have "a PNP transistor",
with its base_emitter path switching the pad to VCC
in case if the voltage on the pad becomes higher than VCC.
//The base of that PNP transistor also works like a resistor between the pad
//and the input of the first inverter.

South from the pad, we have "a NPN transistor",
with its base_emitter path switching the pad to GND
in case if the voltage on the pad becomes lower than GND.
//That's negative voltage.

;---

Note:
the signal from the pad goes through two inverters before it enters the circuitry inside the chip,
the inverters are just a little bit bigger than usual. So I'm ommiting them here.

And that's the part of the story where I have to talk about Latch-up in CMOS chips.

I'm trying to keep things simple and in hobbyist terms,
because that's all you might be going to need for hobby chip dissections.

If you realy want/need to know more, please go down the rabbit hole on wikipedia,
and read Fairchild application note AN-600 "Understanding Latch-UP in Advanced CMOS Logic" 1999.



;---

With NMOS, the game was easy, because we only had NMOS FETs, and the whole chip was "N" ion implanted.

CMOS means "complementary MOS", so we have regions with NMOS FETs and regions with PMOS FETs.
Means that we have regions with "N" ion implantation, and regions with "P" ion implantation.
Let's call these regions "wells".

I think the N and P wells are not quite visible in the microscopic picture of the silicon.
When considering a cross section of the silicon, they are hidden inside the chip,
below the surface.

The visible N and P diffusion layer parts are just "the rocks showing out of the water",
while somehow being part of "the reef" which is a well below the surface of the chip.

I don't know how to identify which diffusion is N and which diffusion is P,
your best bet might be following the metal traces to the power supply pads.
From there, you only can guess where the wells inside the chip might be located.
For more details, please ask Frank.

But now back on topic.
When designing/building hardware, you need to be aware that the parts you are using
have certain physical/electrical characteristics.
And the trick is to make them characteristics work for you and not against you.

When a N well and a P well become neighbors, they form up a diode.
If they form a N-P-N or P-N-P sequence, this gives you a bipolar junction transistor.
Particulary dangerous is NPNP and PNPN, because this gives you a thyristor.

Particularly dangerous, because thyristors are very good at triggering at a transient,
then permanently switching through a lot of current.
If you would have a parasitic thyristor in a CMOS chip layout by accident,
it usually would be sitting between GND and VCC,
waiting for a transient (especially during power_on and power_off)
just to have a reason for blasting the "enabling smoke" out of the chip,
in a cataclysmic event which is called "Latch-up".

Because of this, some effort has to go into preventing thyristors from sneaking
into a CMOS chip layout, but more about this later.

When considering the cross section of a chip, we don't just have
"a little N well here and a little P well there"
like in Bob Ross's "the joy of painting".

When considering the cross section of a chip (and not just the simplified top view),
the arrangement of N and P wells (ion implantation zones) inside the silicon
basically is a Матрёшка thing.


//picture is borrowed from Wikipedia.

Alternatively, you could imagine creatively cramming boxes labeled "N" and labeled "P"
interleaved into one another.

To make sure that no thyristor sneaks in, you need to prevent NPNP and PNPN sequences from forming up,
by creatively making the "wall" of the "outermost box" a diode in reverse direction (biased with GND and VCC).
That's basically the whole trick.

It's nicely visible in the circuitry around the input pads and around the output pads.
For the rest of the logic on the chip I think the game is pretty similar,
it just isn't obvious from the chip layout.

Now for the 5719 output pads,
we now focus on OEB# which has a push/pull output.

Means, that the output driver is switching OEB# eiher to GND or to VCC.

The FETs of the driver are quite big, and there is more than one to GND and VCC,
but basically the pad output driver is just an inverter.

The game of how and why cramming "N boxes" and "P boxes" interleaved into one another
and why making the "wall" of the "outermost box" a a diode in reverse direction
already went explained above in the text.

;---

Note, that there is an inverter which just is bigger than usual
between the circuitry on the chip and the input of an output driver.
I'm just omitting it.

For "open collector" output pads which are only switching to GND,
like the VPA# pad,
we just creatively stick together
"the NMOS FET part of a push/pull output driver switching the pad to GND"
with "the PNP protection transistor of an input pad",
and that's all there is to it.

Now for the logic gates we have found in the chip.

The designers seemed to have used the "copy&paste" approach for building the logic gates,
means that identifying the logic gates is quite easy.

The layout of a gate sometimes is mirrored, rotated by 180°, or both.
//...But never by 90°.

Most of the logic gates on the chip are NANDs,
there are quite some inverters,
there only are two NOR gates,
there are some transparent latches (every latch is built around a 2:1 multiplexer),
and there are three 2:1 multiplexers working as XOR gates.

CMOS inverter is supposed to be simple:

One PMOS FET switching the output to VCC,
one NMOS FET switching the output to GND,
and that's it.

CMOS NAND,
we can imagine that it is based on the CMOS inverter.

Two PMOS FETs in parallel switching the output to VCC,
two NMOS FETs in series switching the output to GND.

I think, you can imagine how to build a NAND with more than two inputs.

CMOS NOR

Two PMOS FETs in series switching the output to VCC,
two NMOS FETs in parallel switching the output to GND.

Since most of the logic gates in the chip were NAND gates,
and there only were two NOR gates in the chip in total,
I think we can assume that CMOS NOR gates have worse
electrical characteristics than CMOS NAND gates.

CMOS transparent latch

It consists of a NAND gate, an inverter, and a 2:1 multiplexer.

Electrically, we can see the 2:1 multiplexer as an "analog SPDT switch".

Actually, said "analog SPDT switch" is built from two transmission gates.
//Also, please take a look at the CD4066 datasheet.

One transmission gate is built from a NMOS FET plus a PMOS FET switching in parallel,
and that's because:
PMOS FETS are good in passing through logic 1, but poor in passing through logic 0.
NMOS FETs are good in passing through logic 0, but poor in passing through logic 1.

However:
PMOS FET needs logic 0 at its gate for switching through,
NMOS FET needs logic 1 at its gate for switching through,
and that's why we need a high_active LD and a low_active LD# signal for controlling the latch.

Also, we have three 2:1 multiplexers (with an inverter attached to the output) in the chip,
which are working as XOR gates.

These 2:1 multiplexers have identical layout like the 2:1 multiplexers we already had in the latch.

;---

A 2:1 multiplexer actually is a quite powerful device:

Consider a two input logic gate.
If the input signals happen to be available both in both high_active and low_active form,
and you creatively wire up the data inputs and the select input of a 2:1 multiplexer,
said multiplexer can replace any type of a two input logic gate.

For more details, see the onsemi NB7L86A datasheet.

//OK, so the NB7L86A 2:1 multiplexer is "differential ECL" and not CMOS,
//but the datasheet nicely describes how to wire it up to make it work as a logic gate.

That's all for now.

8551 is next.
//HMOS-II implementation of the 6551 UART.

Merry Christmas,
and a Happy New Year.