Previous thread: 8521 dissection

This thread is about a transistor level dissection of the MOS 6520 PIA (Peripheral Interface Adapter),
brought to you by Frank Wolf and ttlworks.

6520 features two 8 Bit parallel I\O ports (with handshake).

Note, that the 6520 has two "open collector" interrupt output pads:
IRQA# is related to PORT A, IRQB# is related to PORT B.
Whether you wire them to the IRQ# or NMI# pad of your CPU, that's your choice.

All of the latches in the 6520 are fully static transparent latches built from NOR gates,
so I think that the 6520 won't mind holding/stretching the PHI2 clock.

Like in the 6530, the signal from the PHI2 pad goes unbuffered into a lot of the circuitry on the chip,
so we could expect to have a lot of capacitance to GND at the PHI2 pad.

Note:
For consistence with Frank's notation, low_active signals are named foo#, not /foo.

Orientation for all the chip pictures: VCC pad is North.

;---

First, there were NMOS chips:

MC6820 (Motorola) was an early PIA (Peripheral Interface Adapter), and there is a patent to it. //Bill Mensch
MC6821 (Motorola) was a MC6820 successor with identical functionality.

6520 (MOS) had identical functionality to the MC6821. //Bill Mensch
There were rumors that MOS did a 6521, but we can't confirm this.

Second source manufacturers of 6821\6520 included:
Rockwell, Fairchild, AMI Semiconductor, Hitachi, Synertek, GTE\CMD.

Later, there also was a CMOS successor of the 6520:
G65SC21 (GTE\CMD), R65C21 (Rockwell), W65C21 (Western Design Center).
W65C21 is still in production. //Bill Mensch

All of these NMOS\CMOS chips from different vendors are supposed to have identical functionality,
but the electrical parameters may vary.

So before replacing a chip in an old computer with a different (and maybe less old) chip,
you better take a closer look at the datasheets for both chips.
//The "little differences" between W65C21N and W65C21S etc.

;---

MC6820 was used in pinball machines.
MC6820 was used in the Apple I.
Tandy Color Computer had used two MC6821 for I\O.
6520 was used in Commodore PET and Atari 400\800.

;---

NMOS datasheets:
MOS 6520 preliminary
MOS 6520
Motorola MC6821

MC6820 related patent:
US Patent Number 3,968,478
Inventor: William D. Mensch, Jr., Mesa, Ariz.
Assignee: Motorola, Inc., Chicago, Ill.
Filed: Oct. 30, 1974
//The MC6820 layout in the patent from 1974 appears to be manually routed.

There is a microscopic picture of the MC6820 silicon at Ken Shirriff's site,
but it seems to be from a chip which was manufactured in 1976, and the chip layout looks like routed by CAD.

Wikipedia:
"In 1976 Motorola switched the MC6800 family to a depletion-mode technology
to improve the manufacturing yield and to operate at a faster speed."

Eagle 6.4 schematics for my schematic pictures in this thread,
just in case if somebody needs them.

Note: KiCad is supposed to be able to import these schematics,
unfortunately it doesn't seem to be possible to disable the layers 'name' and 'value' in KiCad schematics,
so making my schematics look nice and clean in KiCad will require some work, sorry.

A picture of the 6520 silicon, with the interesting areas marked.



Just as a reference, another picture of the 6520 silicon without the markings.

6520 cheat sheet:

1a) PHI2 pad

Just the usual ESD protection at the PHI2 pad,
and from there the PHI2 clock signal goes unbuffered and directly
into the circuitry on the chip.

In other words:
The circuitry on the chip is building up quite some capacitance
to GND at the PHI2 pad.

1b) RST#

The low_active RST# signal is used to put the chip into hardware reset.

The signals from the RST# pad goes through the usual ESD protection,
then through an inverter, then into a non_inverting super buffer.

Said super_buffer emits the high_active RST signal,
which then resets the circuitry on the chip.

Note, that RST# isn't synchronized with any clock when it becomes RST.

1c) IRQA#

We have a combination gate which implements two AND gates feeding a NOR gate.

The output of the NOR gate goes into an inverting super buffer,
which drives the FET that switches the IRQA# pad to GND.

IRQA# is an "open collector" interrupt output.

;...

One AND gate is fed with two Bits from CRA (Control Register A):
CRA6 //the CA2 interrupt flag
CRA3 //the CA2 interrupt enable Bit

Note, that when CA2 is configurated as an output by CRA5=1,
the CRA6 CA2 interrupt flag is permanently cleared.

The other AND gate also is fed by two CRA Bits:
CRA7 //the CA1 interrupt flag
CRA0 //the CA1 interrupt enable Bit

So when (CRA6=1 AND CRA3=1),
OR when (CRA7=1 AND CRA0=1),
the low_active IRQA# pad is switched to GND.

1c) IRQB#

//Same game as with IRQA#, it just looks different in the silicon.

We have a combination gate which implements two AND gates feeding a NOR gate.

The output of the NOR gate goes into an inverting super buffer,
which drives the FET that switches the IRQB# pad to GND.

IRQB# is an "open collector" interrupt output.

;...

One AND gate is fed with two Bits from CRB (Control Register B):
CRB6 //the CB2 interrupt flag
CRB3 //the CB2 interrupt enable Bit

Note, that when CB2 is configurated as an output by CRB5=1,
the CRB6 CB2 interrupt flag is permanently cleared.

The other AND gate also is fed by two CRB Bits:
CRB7 //the CB1 interrupt flag
CRB0 //the CB1 interrupt enable Bit

So when (CRB6=1 AND CRB3=1),
OR when (CRB7=1 AND CRB0=1),
the low_active IRQB# pad is switched to GND.

2) CS, R/W#

To make it short:

6520 has two high_active chip select inputs (CS0, CS1) and one low_active chip select input (CS2#).
//Having more than one chip select input could simplify the address decoding logic of a 6502 system.

When CS0=1 AND CS1=1 AND CS2#=0, the chip is selected.

R/W# HIGH indicates read (CPU reads a 6520 register), R/W# indicates write (CPU writes a 6520 register).

The thing is, that _inside_ the 6520, register reads happen during PHI2, in the CPU read cycle.
But register writes happen in the first half of the PHI2 cycle which follows the write cycle.

;...

So we have some logic gates which check whether the chip is selected (maybe with write active) or not.

RD# is the low_active read enable signal.
When the chip is selected during a read cycle (R/W=1), AND PHI2 is HIGH, and RST is inactive,
RD# is active.

WE# is the low_active write enable signal, generated by a RS flipflop (which built from two NOR gates).
The flipflop is set during PHI2 if the CPU selects the chip and does a write cycle.
The flipflop is cleared during PHI2 if the CPU does not select the chip at all.

WE# and RD# go into "4) address decoder".

;---

Also, we have a RS flipflop which generates the high_active CB2_HS handshake signal for the CB2 output.
The flipflop is set in the first half of the PHI2 cycle that follows a CPU PRB write cycle. //Port B data write.
The flipflop is cleared in the first half of a PHI2 cycle when WE# is inactive.

CB2 goes into "12b) CB2 out".

;---

During PHI2 of a CPU PRA read cycle, the CA1 (CRA6) and CA2 (CRA7) interrupt flags are cleared.

R_PRA is the high active PORT A read control signal. //PORT A data read.
It goes together with inverted RD# through an AND gate, sets the RS flipflop which generates
the high_active CLR_CRA67 signal for clearing the CA1 and CA2 interrupt flags.
Said RS flipflop is cleared during PHI2 when the chip is not selected.

CLR_CRA67 goes into "5) CRA".

;...

During PHI2 of a CPU PRB read cycle, the CB1 (CRB6) and CB2 (CRB7) interrupt flags are cleared.

R_PRB is the high active PORT B read control signal. //PORT B data read.
It goes together with inverted RD# through an AND gate, sets the RS flipflop which generates
the high_active CLR_CRB67 signal for clearing the CB1 and CB2 interrupt flags.
Said RS flipflop is cleared during PHI2 when the chip is not selected.

CLR_CRB67 goes into "6) CRB".

;---

3a) A0
3b) A1

For selecting the 6520 registers, the A0 and A1 pads connect to the address lines A0 and A1 of the CPU.

Circuitry for A0 and A1 inside the 6520 is pretty much the same, so we focus on A0.

The signal from the A0 pad goes through the usual ESD protection, then through an inverter,
which feeds another inverter.

Both inverters are feeding two drivers.
One driver emits the high_active A0in signal, //same polarity as A0
the other driver emits the low_active A0in# signal. //A0 inverted.

A0in and A0in# go into "4) address decoder" to be used for register read select.

;...

Again: _inside_ the 6520, register reads happen during PHI2, in the CPU write cycle.
But register writes happen in the first half of the PHI2 cycle which follows the write cycle.

So we have a fully static transparent latch built from two NOR gates,
which samples A0in (and A0in#) during PHI2.

Said latch emits the high_active 2A0in signal and the low_active 2A0in# signal,
which we need during the first half of the next PHI2 cycle.

2A0in and 2A0in# go into "4) address decoder" to be used for register write select.

3c) D7

D0..D7 pads connect to the D0..D7 data bus of the CPU.

Layout for D0..D7 does vary a bit to make better use of chip space,
but at transistor level the circuitry is identical, so we just focus on D7.

At the output side, we have two NOR gates with push/pull output.

RD# and D7out# go into the first NOR gate,
which drives the FET that switches the D7 pad to VCC.

RD# goes into the second NOR gate,
D7out# goes through an inverter into the second NOR gate,
which drives the FET that switches the D7 pad to GND.

RD# is the low_active read control signal, which is generated in "2) CS, R/W."
It is active during PHI2 when the CPU selects the 6520 during a read cycle.

D7out# is the low_active read data bus line inside the 6520.

;---

//We just ignore the usual ESD protection FET.

At the input side, the signal from the D7 pad goes into an inverter,
the output of that inverter goes into "3d) DL7, D7 data input latch".

Physically, DL7 doesn't belong to the D7 pad buffer/driver circuitry,
in the chip layout DL7 looks like just another one of the 6520 registers.
//DL0..DL7 registers are located West of the CRA0..CRA7 registers.

It contains a gated RS flipflop (similar to the RS flipflops in the rest of the 6520 registers),
plus the necessary second inverter at the data input of said RS flipflop.

The RS flipflop works as a fully transparent static latch,
which samples the D7 pad at PHI2,
and gives out the signals on the 6520 internal write data bus lines
D7in (high_active) and D7in# (low_active).

4) address decoder

Low_active register read control signal RD#
and low_active register write control signal WE#
go into the address decoder.
They are generated in "2) CS, R/W".

Read address lines A0in, A1in (high_active)
and A0in#, A1in# (low_active) go into the address decoder.
They are generated in "3a) A0, 3b) A1).

Write address lines 2A0in, 2A1in (high_active)
and 2A0in#, 2A1in# (low_active) go into the address decoder.
They are sampled by transparent latches during PHI2
in "3a) A0, 3b) A1".

//Again: _inside_ the 6520, register reads happen during PHI2, in the CPU write cycle.
//But register writes happen in the first half of the PHI2 cycle which follows the write cycle.

Also, the outputs of the register Bits CRA2 and CRB2
go into the address decoder.



;---

Physically, the address decoder breaks into three parts on the chip.

3a) part 1, located East of the "3a) A0, 3b) A1" latches.
Just some NOR gates which detect CRA (control register A)
reads/writes at address $1,
and CRB (control register B) reads writes at address $3.




;...

3b) part 2, located South of the PORT A circuitry.
Part 2 contains the drivers for the CRA/CRB read/write control signals from 3a).

It also contains the NOR gates for detecting DDRA (data direction register PORT A)
reads/writes at address $0 when CRA2=0,
and for detecting PRA (data register PORT A) reads/writes at address $0 when CRA2=1.

Plus the necessary inverter for the CRA2 signal.

Plus the related drivers for said register control signals.




;...

3c) part 3, located south of the PORT B circuitry.

It contains the NOR gates for detecting DDRB (data direction register PORT B)
reads/writes at address $2 when CRB2=0,
and for detecting PRB (data register PORT B) reads/writes at address $2 when CRB2=1.

Plus the necessary inverter for the CRB2 signal.

Plus the related drivers for said register control signals.




;---

The register read/write control signals which are generated in 4a)..4c) go up North
into the register block.

Note, that there is a FET somewhere up North in the register block
for every register write control signal, switching said signal to GND during PHI2.

We have seen similar things in the 6530 and the 6522.
The designers just wanted to be on the safe side that said control signals
really are disabled during PHI2.

Also note, that register write signals go active with a delay of maybe two logic gates
after the falling edge of PHI2.
This was done because the transparent latches which sample A0 and A1 at PHI2,
generating the write address signals, need some time to have their outputs stable.

BTW: all of the register read/write control signals which are generated
in 4a)..4c) are high_active.

Chip layout for 4b) and 4c) somehow reminds me a little bit to the
address decoder we already had in the 6522 dissection.

5a) CRA0..CRA5, control register A

CRA0..CRA5 register Bits are used for controlling PORT A:
CA1, CA2, and the INTA# interrupt output.

Layout for the CRA0..CRA5 register cells is pretty identical, so we focus on CRA0.

Basically, the CRA0 register Bit is built around a gated RS flipflop.

When high_active register write control signal W_CRA is active,
the 6520 internal write data bus lines D0in and D0in# are used
to set/clear the RS flipflop.

The RS flipflop also asynchronously is cleared with RST during a hardware reset.

The high_active output of the RS flipflop goes together with the
high_active register read control signal R_CRA into an "open collector" NAND gate.

The output of said NAND gate connencts to the 6520 internal low_active
read data bus line D0out#.

CRA5 has an additional inverter attached to its high_active output,
generating the low_active CRA5# signal.

//CRB5 lacks that inverter, because the inverter for CRB5 is part of "12b) CB2 out".



;---

5b) CRA6

CRA6 is the CA2 interrupt flag.
It is built around a RS flipflop.

The RS flipflop is set by high_active signal SET_CRA6,
which is generated by the edge detector in "10a) CA2 in" in case there is an active edge at CA2.

The RS flipflop is cleared when RST is active.
Also, it is cleared when CA2 is configurated to work as an output by CA5=1,
or by high_active signal CLR_CRA67 which is generated in "2) CS, R/W#"
during a PRA read.

Like with CRA0..5, CRA6 can be placed on the low_active 6520 internal read data bus line D6out#
by high_active register read control signal R_CRA and an "open collector" NAND gate.

;---

5c) CRA7

CRA7 is the CA1 interrupt flag.
It is built around a RS flipflop.

The RS flipflop is cleared when RST is active.
Also, it is cleared by high_active signal CLR_CRA67 which is generated in "2) CS, R/W#"
during a PRA read.

The RS flipflop is set by high_active signal SET_CRA7,
which is generated by the edge detector in "9) CA1 in" in case there is an active edge at CA1.

Like with CRA0..5, CRA7 can be placed on the low_active 6520 internal read data bus line D7out#
by high_active register read control signal R_CRA and an "open collector" NAND gate.

6) CRB, control register B

Similar game like with "5) CRA".
Just for PORT B: CB1, CB2 and the INTB# interrupt output.

Again, we have a RS flipflop for CRB6, and another RS flipflop for CRB7.

R_CRB and W_CRB are the high_active CRB register read/write control signals.

CRB6 and CRB7 are cleared with high_active signal CLR_CRB67 which is generated
in "2) CS, R/W#" during a PRB read.

CRB6 is the CB2 interrupt flag, it is set by high_active signal SET_CRB6
which is generated by the edge detector in "12a) CRB2 in" in case there is an active edge at CB2.
When CB2 is configurated to work as an output by CRB5=1,
CRB6 is permanently cleared.

CRB7 is the CB1 interrupt flag, it is set by high_active signal SET_CRB7
which is generated by the edge detector in "9) CB1 in" in case there is an active edge at CB1.

Note:
The pullup FETs for the 6520 internal D0out#..D7out read data bus lines
are part of CRB.

7) PA0 //PORT A

8 Bit I\O port, with "open collector" outputs and pullup FETs to VCC.

Layout for PA0..PA7 is similar, with some variations to make better use of chip space,
so we just focus on PA0.

;---

First for the output side:

DDRA0 (data direction register A) configurates,
whether PA0 works as an input (DDRA0=0)
or as an output (DDRA0=1).

It is cleared by RST during a hardware reset, defaulting PORT A to input.

DDRA0 is built around a gated RS flipflop.
High_active register write control signal W_DDRA clears/sets DDRA0
according to the 6520 internal write data bus lines D0in and D0in#.

The high_active output of DDRA0 goes together with high_active register read control signal
R_DDRA into an "open collector" NAND gate, with the output connected to the low_active
6520 internal read data bus line D0out#.

;...

The PRA0 (PORT A) data output register is built around another RS flipflop.

High_active register write control signal W_PRB clears/sets the PRA0 register
according to the 6520 internal write data bus lines D0in and D0in#.

The RS flipflop is cleared by RST during a hardware reset.

The inverted output of DDRA0 and the non_inverted output of the PRA0 register
go into a NOR gate, which feds a non_inverting super buffer.

Said super buffer drives the FET which switches PA0 to GND.

Means when DDRA0=1 AND the PRA0 register is 1, PA0 is switched to GND.

;---

Now for the input side:

PA0 pad has ESD protection and a pullup FET,
the layout of that part just looks a little bit unusual.

After the ESD protection the signal from the PA0 pad goes through two inverters,
then together with the high_active register read control signal R_PRA into
an "open collector" NAND gate, with the output connected to low_active 6520 internal
read data bus line D0out#.

But be aware:
If you have a glitch on PA0 when reading PRA0, that glitch shows up on the 6502 data bus, too.
For better signal integrity, I would suggest to sample PA0 by a transparent latch
during PHI2=0 when building your own TTL or FPGA implementation of the 6520.

Also, you need to be a bit paranoid about the capacitive load on PA0,
like when using read/modify write instructions aiming at PRA,
because pullup FET plus capacitive load delay the rising edge on PA0.
//same thing for PA1..PA7

And you need to be aware that PA0 could be switched to GND by circuitry outside of the 6520.