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PostPosted: Wed Nov 23, 2022 4:55 pm 
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Hello everyone.

Small poll / feeler: who uses the new WDC opcodes in the $_7 and $_F columns? Those include RMB, SMB, BBR, and BBS instructions? I personally have never used them.

Im not asking hypotheticals on *why* to use them. Im just flat out asking if you actually use them, and in what.

Reason for this is Dr Jefyl is suggesting a fix for a board Im working on, and removing the (typical) use of those instructions would be one way to fix it.

viewtopic.php?f=4&t=7407

I could have interpretted him incorrectly, but it I think this would fix the issue anyways. Im not asking to look at my other topic necessarily, just if you use these newer instructions or not.

Thank you everyone!

Chad


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PostPosted: Wed Nov 23, 2022 5:30 pm 
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the Video Card i've been working on will have a 65c02 as co-processor on it, so i mapped it's IO into the ZP so i could make use of those instructions for slightly more compact code.
example from the Video CPU's Boot code that sits inside a small 128B ROM:
Code:
get_byte:                       ; Bit 7 is the Empty Flag of the Receiving (RX) FIFO
    BBS7 STATUS, get_byte       ; Loop for as long as it's 1 (ie FIFO has no Data in it)
    LDA RX_FIFO                 ; Once it's 0, read a Byte from it
RTS


I'll have to see how much of a difference that's gonna make


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PostPosted: Wed Nov 23, 2022 5:52 pm 
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Well, as soon as Rockwell released their R65C02 in the 80's, I bought a couple (still have them) and have been making good use of the extended instructions and addressing modes ever since. My current C02 Monitor and BIOS use the bit set (RMB, SMB, BBSx, BBRx) instructions quite a bit. Those allow a single page zero location to serve as 8 separate flags that can be set, reset and tested/branched on, which is quite helpful.

I also use all of the stack instructions (PHX, PHY, PLX, PLY), the STZ opcodes, JMP (addr,X) and other enhancements to the indirect addressing modes. For examples of many of these, just grab my current C02 Monitor and BIOS code from github. They can save memory space and in many cases code execution time as well.

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PostPosted: Wed Nov 23, 2022 10:17 pm 
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sburrow wrote:
Small poll / feeler: who uses the new WDC opcodes in the $_7 and $_F columns?

Just to be clear, these instructions only apply to the 65C02.

Also note that the “bit-twiddlers” (BBR, BBS, RMB and SMB), aka “Rockwell extensions”, are not “new WDC opcodes,” despite what the 65C02 data sheet says. They are instructions that Rockwell, who was the first licensee of the 65C02 design, added after they started using the 65C02 in modem applications. Bill Mensch’s original 65C02 design did not have them—they all mapped to NOPs.

Other licensed producers of the 65C02 could not include the Rockwell extensions into their renditions of the 65C02 due to licensing restrictions, as they were proprietary to Rockwell’s product. This created the undesirable situation of there being incompatible versions of the same device on the market. WDC subsequently added the Rockwell extensions to the basic design, which made it legal for other licensees to produce MPUs with them.

Note that the Eyes & Lichty programming manual doesn’t mention the Rockwell extensions anywhere in the main text. They are relegated to an appendix, since at the time the manual was written, those instructions weren’t part of the official 65C02 assembly language.

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Those include RMB, SMB, BBR, and BBS instructions? I personally have never used them.

That’s two of us, and I used to do a lot of 65C02 development back in the 1990s.

The main limitation of the BBx and xMB instructions is they only work on zero page, which hampers their generality. Furthermore, the xMB instructions can only clear/set one bit at a time. Contrast that with TRB and TSB, which can operate on an arbitrary number of bits, plus have both zero page and absolute addressing modes, making them more useful in most applications.

Lastly, consider that a 65C02 program using BBx and xMB cannot be run on a 65C816, even in emulation mode.

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PostPosted: Fri Nov 25, 2022 10:00 am 
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I have never used the 65C02 instructions - a large fraction of my 6502 experience was NMOS, and I haven't seriously used the 65C02.

However, my 65020 extension has equivalent instructions, which I use a lot more often than I was expecting to. Their main use is for packing a number of flags into a single byte, like floobydust explains.

My version can access any byte in memory, which makes them good for testing/manipulating status/control bits in IO registers as well.


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PostPosted: Fri Nov 25, 2022 1:41 pm 
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I used BBR0-3 in my university project.

Basically, I had the input buttons wired up to a shift register which was fed in and then run through a debounce routine. It'd end up with a byte in Page0 with a bit set to '1' for each button that had been newly pressed. Used BBRx to branch over the processing code for each button if they were not pressed.

Could I have done it another way? absolutely, but as I had control over where this byte value was to be located, it was convenient to use BBR. Also a design goal of the project was to exercise as much of the instruction set as possible, so this helped achieve that, too.

relevant code snippet...
Code:
    ; User input has changed
    AND     <ButtonNew      ; Now A contains '1' for Positive Edge Button events only.
    STA     <ButtonOld      ; ButtonOld is out of date anyway, so re-use it to store above value.
   
    ; Take Heap 1
    BBR0    <ButtonOld, ?SkipTakeHeap1  ; If bit 0 clear, user has not pressed Take on Heap 1
    LDA     <HeapSelect     ; If HeapSelect = 2 or 3, don't decrement.
    CMP     #2
    BEQ     ?SkipTakeHeap1
    CMP     #3
    BEQ     ?SkipTakeHeap1
    LDA     <Heap1          ; Don't decrement or record selection if Heap 1 isn't zero.
    BEQ     ?SkipTakeHeap1
    LDA     #1              ; Record that player has selected heap 1
    STA     <HeapSelect
    DEC     <Heap1          ; Decrement Heap.
?SkipTakeHeap1:

    ; Take Heap 2
    BBR1    <ButtonOld, ?SkipTakeHeap2  ; If bit 1 clear, user has not pressed Take on Heap 2
    LDA     <HeapSelect     ; If HeapSelect = 1 or 3, don't decrement.
    CMP     #1
    BEQ     ?SkipTakeHeap2
    CMP     #3
    BEQ     ?SkipTakeHeap2
    LDA     <Heap2          ; Don't decrement or record selection if Heap 2 isn't zero.
    BEQ     ?SkipTakeHeap2
    LDA     #2              ; Record that player has selected heap 2
    STA     <HeapSelect
    DEC     <Heap2          ; Decrement Heap.
?SkipTakeHeap2:

    ; Take Heap 3
    BBR2    <ButtonOld, ?SkipTakeHeap3  ; If bit 2 clear, user has not pressed Take on Heap 3
    LDA     <HeapSelect     ; If HeapSelect = 1 or 2, don't decrement.
    CMP     #1
    BEQ     ?SkipTakeHeap3
    CMP     #2
    BEQ     ?SkipTakeHeap3
    LDA     <Heap3          ; Don't decrement or record selection if Heap 3 isn't zero.
    BEQ     ?SkipTakeHeap3
    LDA     #3              ; Record that player has selected heap 3
    STA     <HeapSelect
    DEC     <Heap3          ; Decrement Heap.
?SkipTakeHeap3:

    ; Done Button
    BBR3    <ButtonOld, ?SkipDone  ; If bit 3 clear, user has not pressed Done
    LDA     <HeapSelect     ; Check if player has done at least one by checking HeapSelect.
    BEQ     ?SkipDone       ; If HeapSelect=0, cannot go to next player's turn.
    JSR     CheckVictory    ; Check if the player has won. If they have, CheckVictory does not return.
    LDA     <Turn
    BEQ     ?TurnIsGreen    ; If Z=1 then Turn=0, hence Green.
    LDA     #$FF            ; If turn was 1 (red), overwrite A with FF so that INC A gives 0 (green).
?TurnIsGreen:
    INC     A               ; If TurnIsGreen, A now=1 hence RED. If not, A now=0, hence GREEN.
    STA     <Turn
    STZ     <HeapSelect     ; Clear HeapSelect
?SkipDone:



Also, on the WDC Microcontroller W65C134 these instructions are extremely useful as all the built-in I/O registers are mapped to Zero Page. I haven't actually written any software yet (still doing the hardware design), but I very much intend to make liberal use of these instructions on my current project that is designed around the '134.

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PostPosted: Fri Nov 25, 2022 7:37 pm 
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Similar topics are:
65c02 advantages
Pervasiveness of 65c02 instruction set versus the original.

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PostPosted: Sat Nov 26, 2022 4:58 am 
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There's so many ways the additional instructions and addressing modes can help reduce code size and execution time. I just started a different port of DOS/65 for a disk bootable version. I just pulled the CCM and PEM modules out of the SYSGEN code for Version 3.02 and got those into my usual build setup (WDC Tools) which didn't require much work. Just for comparison... the PEM module with it's variables assembled to 3024 bytes. With a fair amount of reworked routines, I got it down to 2800 bytes and can reduce it further if I want to use more page zero space, which I'm trying not to do. The CCM module with it's variables was 2369 bytes, but is now 2250 bytes... but I'm going to take another dive into the CCM source and see what else I can target.

In any case, unless you are purposely writing code to run on old machines using the NMOS CPU (which also means it's pretty slow), I can't find any reason not to leverage the CMOS extensions when writing code.... just my $0.02.

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PostPosted: Sat Nov 26, 2022 1:10 pm 
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The w65c134s, according to WDC’S data sheet, doesn’t include Rockwell bit manipulation op-codes.


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PostPosted: Sat Nov 26, 2022 1:30 pm 
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the W65C134S datasheet is weird. for example it mentions that has both a "W65C02S compatible CPU" and is "W65C816S 16-bit CPU compatible"
and i'm not sure how either can be true since it's aparently missing instructions from the W65C02, and is almost definitely not a W65C816 in disguise
it also says it has a "16M byte segmented address space", so is it actually a 65C816 in disguise, or does it have some kind of built-in MMU or bank switching?


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PostPosted: Sat Nov 26, 2022 11:23 pm 
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Thank you everyone for the insights. Just learning here, I appreciate the replies!

Chad


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PostPosted: Sun Nov 27, 2022 10:05 am 
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The W65C134S datasheet doesn't mention what instructions it supports at all, it just links to the W65C02S datasheet, which includes the Rockwell instructions. Therefore without concrete evidence to the contrary I assume it has all the instructions the (modern) W65C02S does.

That being said, I had a gander at the built-in ROM's listing, and it includes CMOS instructions and modes, but no Rockwell or '816 instructions. So unfortunately inconclusive. It would be strange for the built-in ROM not to use the Rockwell BBx and xMB instructions given that the I/O is in zero-page, but perhaps the ROM was programmed before WDC started including the Rockwell instructions in their CPU cores? Or, as I recall, there was a time when you could buy the WDC chips with or without the Rockwell extensions, so perhaps the ROM was programmed to be compatible with both versions of the '134 (if such versions existed).

Honestly, though, the '134's datasheet is frustratingly bad. I am fully aware WDC's documentation is.... not great, but the '134 is a new level of bad. Missing or conflicting information, typos in key places...

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PostPosted: Mon Nov 28, 2022 2:51 am 
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Alarm Siren wrote:
I had a gander at the built-in ROM's listing, and it includes CMOS instructions and modes, but no Rockwell or '816 instructions [...] so perhaps the ROM was programmed to be compatible with both versions of the '134 (if such versions existed).
Perhaps the routines used in the ROM were intended to be compatible with both the '816 and the 'C02.

Quote:
Honestly, though, the '134's datasheet is frustratingly bad. I am fully aware WDC's documentation is.... not great, but the '134 is a new level of bad. Missing or conflicting information, typos in key places...
<sigh> Disappointing, but this news doesn't come as a surprise.

- Jeff

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PostPosted: Tue Nov 29, 2022 10:50 am 
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Proxy wrote:
the W65C134S datasheet is weird. for example it mentions that has both a "W65C02S compatible CPU" and is "W65C816S 16-bit CPU compatible"
and i'm not sure how either can be true since it's aparently missing instructions from the W65C02, and is almost definitely not a W65C816 in disguise
it also says it has a "16M byte segmented address space", so is it actually a 65C816 in disguise, or does it have some kind of built-in MMU or bank switching?

I second you - the datasheet is weird.

But if you take "W65C02S compatible CPU" AND "W65C816S 16-bit CPU compatible" as logical AND (not arithmetic plus) then none of the instructions the (current) W65C02S has but the W65C816S not NOR any instructions the W65C816S has but the W65C02S not are left.

That results in a (historic) W65C02 without later added extensions (Rockwell & WDC). See attached DS.

Cheers
Arne


Attachments:
W65C02-1990-02.pdf [2.32 MiB]
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PostPosted: Tue Nov 29, 2022 2:39 pm 
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Nice find Arne. I grabbed my Rockwell datasheet I received from them in 1984 and scanned it in. Attached here... shows the CMOS extensions and such.

Attachment:
Rockwell R65C02 Datasheet.pdf [13.12 MiB]
Downloaded 70 times


As for the BBRx and BBSx branch instructions, the Eyes/Lichty manual does not show the extra clock cycles when the branch is taken, which is 1 more for branching on the same page and 2 more for branching to a different page. These instructions do not alter any processor status register flags either, where the Eyes/Lichty manual shows one being affected on the BBSx instruction.

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