The label of "30ns" for Access Time (tACC) is a little misleading given that the diagram is labelled with timings for 1MHz operation. tACC is the minimum time the CPU allows between providing a valid address (and R/W etc.) and needing valid data available from the external device. Another way of thinking of tACC is the maximum time available for address decoding and memory (or other device such as a VIA) to respond with data. As such, tACC is both voltage AND frequency dependent.

tADS is derived from Cycle Time (tCYC), Address Setup Time (tADS) and Read Data Setup Time (tDSR): tACC = tCYC - tADS - tDSR. So at 14MHz and 5V, tADS = 70ns - 30ns - 10ns = 30ns (which matches the value on the datasheet.) However, at 1MHz and 5V, tCYC is 1000ns so tACC = 1000ns - 30ns - 10ns = 960ns. There are up to 960ns available for address decoding and data access.

I think "960ns" would be a more appropriate label for tACC on this diagram which is labelled with a 1000ns cycle time. Great idea for the consolidated diagram, by the way.