BigDumbDinosaur wrote:
In looking over the second schematic page with the interface to the micro drive, it appears that reading or writing the device is a two-step process due to the 16-bit interface ATA bus. I’m inferring this from the presence of the two 573 latches. Is that correct? Can you edify your audience on how the interface works?
The design was the result of pouring over the Seagate ATA interface reference manual for too many hours!
In short, sending commands and getting status from ATA devices are all 8-bit. The only 16-bit transfers are for data, either reading or writing all 16-bits at once. There is a feature you can set for 8-bit data transfers, but what fun is that? The device default is 16-bit data transfers.
The '573 latches are wired inversely to one another. In the schematic, the lower latch, U2, has it's inputs wired to the upper 8-bits of the Microdrive. The latched output of U2, is wired to the CPU data bus. This is reversed with the upper latch, U3, which has it's inputs wired to the CPU data bus and it's latched outputs wired to the upper 8-bits of the Microdrive.
The timing is such that, when a read operation is performed, U2, latches the upper 8-bits of data. So at the same time the CPU reads the lower 8-bits, the upper 8-bits get latched. The CPU then reads the latch to get the upper 8-bits. The write operation is done opposite. The CPU has to write the upper 8-bits of data to latch U3 first, then writes the lower 8-bits of data to the Microdrive. When the write operation to the drive is performed, U3 is also selected to present the latched data on the upper 8-bits of the drive.
All of the decoding and timing is done via the ATF16LV8 PLD. It does two functions: First, it takes a single 32-byte wide I/O select and decodes that into the chip select for the RTC, the two register select lines for the Microdrive and decodes two addresses for the latches. Second, it generates timing signals to control the 4 lines of the two latches. The timing to drive the latches is coupled to the Microdrive Read and Write operations, meaning they (the latches) are only driven in one direction when the Microdrive Data Register is accessed. One is driven to latch during a read operation and the other is driven to present it's latched during a write operation. The latches can be read for one and written to the other separately at their own I/O address.
Below is the CUPL code for the PLD:
Code:
Name IDE-RTC ;
PartNo 01 ;
Date 1/04/2020 ;
Revision 01 ;
Designer KM ;
Company Analogue Technologies ;
Assembly SBC2 ;
Location ;
Device G16V8MS ;
/* *************** INPUT PINS *********************/
PIN 1 = CLK ; /* */
PIN 2 = A0 ; /* */
PIN 3 = A1 ; /* */
PIN 4 = A2 ; /* */
PIN 5 = A3 ; /* */
PIN 6 = A4 ; /* */
PIN 7 = !MRD ; /* */
PIN 8 = !MWR ; /* */
PIN 9 = !SEL ; /* */
PIN 11 = !OC ; /* */
/* *************** OUTPUT PINS *********************/
PIN 18 = !UBWE ; /* */
PIN 16 = !UBRE ; /* */
PIN 19 = UBWL ; /* */
PIN 17 = UBRL ; /* */
PIN 12 = !CS0 ; /* */
PIN 13 = !CS1 ; /* */
PIN 15 = !RTC ; /* */
PIN 14 = !HBT ; /* */
/** Declarations and Intermediate Variables Definitions **/
FIELD ADDRESS = [A4..0];
RTC = SEL & ADDRESS:['h'00..13];
HBT = SEL & ADDRESS:['h'14..15];
CS1 = SEL & ADDRESS:['h'16..17];
CS0 = SEL & ADDRESS:['h'18..1F];
/** Logic Equations **/
UBWE = MWR & SEL & ADDRESS:['h'18..18];
UBRE = MRD & SEL & ADDRESS:['h'14..14];
UBWL = MWR & SEL & ADDRESS:['h'15..15];
UBRL = MRD & SEL & ADDRESS:['h'18..18];
There are 5 address lines that are routed to the PLD as inputs, along the I/O select to Pin9, the decoded Read and Write lines from the C02 Pocket and the CLK line (which isn't used. as the Read and Write lines are clock aligned)... hardware safety feature
- The RTC needs 19 addresses which are not contiguous... the first 17 are, the other two are spaced up by two, so the chips select decodes 19 addresses for it.
- The Microdrive has two chip selects, one for the main set of registers, which is a total of 8. The second select only has 2 registers.
- The latches are assigned two I/O addresses, one or read and one for write.
The hex addresses above show the logic for the latches.The Microdrive Data register is at an offset of hex 18. The latches are at an offset or hex 14 and 15. The latches are selected only when the Microdrive Data Register is selected, one to latch data in during a read and the other to present latched data to the Microdrive during a write. The latches can be accessed separately at address offsets hex 14 and 15 to either read data from one, or write data to the other. It's actually pretty simple for timing.
The BIOS simply has an extra read cycle to get the upper 8-bit of data. Writing requires that the upper-bits are written to the latch first, then the write operation to drive.
The reason behind implementing the 16-bit port is for performance. This becomes more advantageous when you have a CPU clock that is running faster than the ATA design spec can handle (per documentation, is 8MHz). You can add wait states when accessing the drive on reads or writes, then move the data around at higher CPU clock rates. With an 8MHz CPU clock (and no wait states in this design), I can obtain data transfer rates around 360KB/second on a read and around 320KB/second on a write.
This same interface can drive a compact Flash as well, which I did initially. I switched to the Microdrive for some specific reasons:
- physically smaller than a CF Card... with a larger space advantage when you include the socket for the CF Card.
- Being rotating media, you don't have wear-leveling and varying data rates on write operations.
- Being a true IDE device, multiple block reads and writes are supported.
- Testing has shown overall performance to be better than Compact Flash and more consistent (onboard caching for read and write)... but yes, there is still rotational latency.
Hope this explains it...
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