Hi everyone!

What is the purpose of the 6502's PHI2 falling edge Hold Time on the address and data bus? Is that when it is performing internal operations?

I know this is a terribly stupid question, but let's just say for 1 year now I've just passed over this tiny fact.

Thank you all.

Chad

The hold time, on an output, is something I prefer to call the clock-to-Q time. It's a promise that the device driving the bus won't yank the values away too quickly after the clock edge. This promise should then line up with the devices receiving the data - they will have a hold time as a constraint.

In other words, the things receiving promise to operate correctly if the data isn't taken away too quickly, and the things sending promise not to take the data away too quickly.

Sometimes a hold time constrain is zero nanoseconds. This is still meaningful, because the clock which the receiving device sees might be slightly delayed or advanced compared to the clock which the sending device sees.

Overall, inputs have constraints, on how late a signal might arrive (not too late) and how early a signal might cease to be valid (not too early). And outputs have promises, on how late a signal might become valid, and how soon it might cease to be valid.

Note that when a sending device stops driving a signal, the signal doesn't necessarily change - that depends on whether anything else is driving. If nothing is driving, the signal may remain at a valid voltage for a short while. Conversely, if some other sending device starts driving before the first one has stopped, the signal may change and become invalid even before the first one stops driving.

Thank you Ed. Right, a promise, that is good, I understand. But now, sometimes the 6502 is reading data, so it's the receiver. PHI2 falls and... does it still need that data from the RAM/ROM for the "holding time"? I had *figured* (which is never a good thing) that it had already done it's job before the end of PHI2-high. I'm probably wrong.

Thoughts?

Chad

When the CPU is reading data from memory or other peripheral it has a hold time constraint. I believe it is 10ns minimum for a 1MHz or 2MHz old school NMOS 6502. That means the device driving the data bus must keep the data stable for at least 10ns after Phi2 falls.

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Bill

Perfect! Thank you, that's the confirmation I needed.

Thank you both!

Chad

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

So as long as the addressed device at least goes Hi-Z at the fall of Phi2 and there is not anything else to gum up the works there should be no issues? That makes sense. Being the end of a read cycle there is not likely to be anything else driving the bus unless there is some real stiff buss termination, or a badly timed reflection.

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Bill