It turned out that the core had several more apparent errors. Unfortunately, we
were not expecting to require debugging the CPU because it was obtained directly from
the original manufacturer. When we started seeing errors very deep into the project, it
took us very off guard. For example, the Rotate Right (ROR) instruction gave incorrect
answers in several cases. A couple of instructions did not set the condition codes when
they were supposed to, or had timing problems such that they received the condition
codes from a different instruction. There were major bugs with the JSR instruction in the
absolute indexed indirect addressing mode. It saved the wrong address on the stack,
and then jumped to the wrong location.
It certainly looked like the errors that we found were coming from inside the CPU
and not from some interaction with our system. We expect that the WDC would have
informed us if the core was incomplete or untested. Also, there was a previous group
(the SNES) which used the same core but did not mention any errors in their report.

In Verilog, using WDC's soft core [...]

So any bugs would be either in WDC's soft core - at that time - or possibly in the surrounding design or the toolchain.