gfoot on Thu 6 Oct 2022 wrote:
It's always seemed a rather complicated arrangement to me, it may be possible to do it more concisely.
Nowadays, it is trivial to find circuit diagrams for a dozen similar designs. In the the late 1970s and early 1980s, it was incredibly difficult to obtain information quickly or at all. Regardless, there is something distinctly "don't touch it, it's doing something" about Acorn's video circuitry. Despite tear-downs of rival designs, they persisted with a video circuit which has more components than a Sinclair ZX Spectrum. There is also a computer history video where Chris Curry explains that only one brand of tri-state buffer worked for the DRAM address lines. (I have no idea why they didn't use 74LS157, like the Spectrum.) Chris Curry also explained that TTL loads were exceeded by using a data bus pull-down resistor pack to simulate holding a finger to the board. (They only made 1.5 million of these things.) Other parts of Commodore and Acorn designs are crufty because they simultaneously use spare logic gates while skewing 8MHz clock or similar into a 150ns DRAM Row Address Strobe.
I solved this problem as unsolicited work for the Commander X16 project. I thought this would be particularly useful because it would allow 6522 timers to work independently of processor speed. This would solve a minor problem with PS/2 keyboard not working above 2MHz. It would also be useful for the multiple sound outputs and MIDI. (The 8 Bit Guy who started the Commander X16 is very enthused about 8 bit music and 1980s synthesisers.) I was surprised that my work was rejected, although it works best if the slow I/O range is contiguous. I don't believe that yet another suggestion to change the memory map (or 65816 compatibility) was appreciated. Whatever. I gave them first refusal and I'm not offended that they refused.
I solved this problem in a manner which is NMOS or CMOS compatible and works at arbitrary ratios, including ratios which are not integer. This is not original. I believe similar circuitry can be found in Amstrad computers before it became common in x86 designs. It is also highly likely that I have re-invented a subset of CMD SuperCPU functionality. Anyhow, after going slowly mad over three days, I eventually defined the scope of the problem in a manner in which the answer is trivial, one day to ensure that it resets into a useful state and one further day to check my work.
The solution is to use three flip-flops to implement a three state, one-hot, edge triggered state machine where one state is the idle state and the other two states allow the buses to mesh for a sufficiently long period to reliably convey a read or write. The tricky part is that each state inhibits the previous state and therefore the states only advance in one direction. (I strongly doubt this design principle scales gracefully.) Acorn's NMOS design is crufty, uses one unnecessary chip, only works in a 2:1 ratio and was re-designed for CMOS. However, they didn't have my hindsight or five days to work on the problem.
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