I found this 8 Bit binary Calculator on Hackaday:

http://hackaday.com/2009/09/16/8-bit-bi ... /#comments

http://jeff.m.hopkins.googlepages.com/calc

http://picasaweb.google.com/jeff.m.hopkins/Calculator#

The only thing I can compare it to is the Big Mess of Wires project. I suppose it can be used to teach the fundamentals in some way.

That reminds me of this Lego mechanical calculator:
http://www.youtube.com/watch?v=SYi9sJkS19Q

Just a bit faster though.

Neat projects!

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Bill

Is this possible in 6502 machine language?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

What, synthesizing the image of the operating Lego computer? Maybe Tony can tell us. He's the resident arcade expert. But for just doing the calucations, sure. In fact if you put a Forth kernel on your 6502 machine, you can do the math in base 3 or 7 or 11 or any other base just as easily as you can in base 2, 10, or 16. It won't care.

The 6502 has AND and ORA assembly commands.... I've not looked into XOR, but it was one of the IC's used for the hardware calculator... I was just wondering... I need to do 8 bit averaging in my project is why I am interested.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Exclusive OR instruction is the EOR instruction.

BLUSH. Anyhoo, I dont see why it cannot be done. Used to have one of the original digicomps but yup, do a graphics, positions set in flags and apply proper mathematical rules to it. Good times....

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"My biggest dream in life? Building black plywood Habitrails"

I have wanted to build a TTL logic based four function calculator with memory with 74XX ICs for quite some time, this looks like a great place to start!

So I ran across this post when searching google.... I'm actually the guy who built this, and I can appreciate you guys actually making a topic for it here.

If you are a little more interested I've been working on a full 74HC series processor. As of right now the ALU is complete, and the designs for control logic is being finalized in simulation before actual construction. Microcode examples and other information can be found at:

Jeff Hopkins: CPU

Very interesting stuff. Someone else on this forum has made a 6502 processor completely out of discrete TTL logic. Seems to me this is grass roots designing, and a great way to start and possibly redesign/modify a CPU. How do you guys go about designing this stuff? What tools do you use?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

It's surprisingly easy if you start out simple.

Suppose you have two TTL 8-bit registers. To this, you wire up an 8-bit adder circuit, 8-bits of NAND, 8-bits of NOR, and 8-bits of XOR, all in parallel. Whenever any one of the two registers is loaded, all four results are computed in parallel.

To control which one of those results goes back on the bus, you need a multiplexor.

So, you have two register-load signals, and a multiplexor select signal, something around 4 or 5 wires. These wires need to be driven according to a fixed sequence, depending on what instruction you're executing.

One way to do this is through microcode, where the instruction itself forms (just to pick numbers out of the air here) bits 4 through 11 of the microcode's ROM address bus. Bits 0 through 3 are taken from a counter, which gets reset to zero every time the instruction register is loaded. Note that this limits your instructions to 16 clock cycles max.

The output of the ROM's data pins can be connected to these control inputs to sequence the operations accordingly.

A more sophisticated way involves the logic array approach, which replaces the microcode ROM with a matrix of AND-OR-INVERT logic, and address counters with a ring counter. This takes more logic, but it runs faster and, if implemented in silicon, takes up less space thanks to minterm re-use.

That's pretty much it. Everything else is a glorified extrapolation (costing more logic, of course) of these basic concepts, including pipelining, superscalar execution, and so on.

My motivation is to find other alternatives to what is out there. Chip design shouldn't be left to those with billion dollar labs.

I would like to see more applications as I am sure they could be put into FPGA.

I think that some of your ideas could be applied for graphic routines and so forth. Your ideas could be implimented in a graphics chip or processor as I have seen what the Max II can do.

http://www.youtube.com/watch?v=k_E6goZTesM

Bacground:

http://forums.parallax.com/forums/defau ... 426960&p=1

The problem is, to spin about 50 or so development chips, you need to invest $500K in the fabrication costs. And, if you find an error in your chip design, that's another $500K to "re-spin" the chips. I'm sure things get cheaper as you go into volume production, or else you'd never have $0.33 555 chips.

DESIGNING chips is very cheap indeed -- it literally costs nothing these days (SPICE to simulate analog designs, Verilog to implement digital designs, both of which runs on commonly available home computers). It's the actual manufacture thereof that takes the big bucks, because it's labor intensive, deals with vast quantities of hazardous materials (the processing of which must be strictly controlled to avoid environmental contamination, as is what happened with Commodore Semiconductors, prompting them to close a fab and switch to all-CMOS designs; hence the C64C and C128 using the 85xx series of chips), and of course consumes insane amounts of power.



The links you provided are not terribly impressive in the context of "what can be done." I'd rate that merely as a nice teaser.

Consider the "Minimig", which implements the Amiga's chipset on an FPGA, able to render 60fps video, sporting 8 sprites, having a blitter for 2D acceleration, and a video timing coprocessor so you can tweak registers not just every frame, but at arbitrary points within the frame too.

And, the other thing is that folks can implement their own variations on the 6502 theme as well. I, for example, would love to see a 6502-type CPU expanded to 32-bits as per Garth's conception. But, I want to go further than this: I also want to see it support an internal cache, so that I can tweak the address generation so that instructions execute in a single-cycle (when used with a three or four stage pipeline), and so that it lets me crank up the CPU clock speed to above that used by the front-side bus.

I'm still interested in this idea. We know the T65 can be brought to life - bound did it recently. A modest FPGA will have lots of room on-board to add a caching memory interface, and I agree that it could be quite attractive to do that. I would still want to start small: a T65 6502 first, then a 65Org16, then perhaps a fancy memory interface, or perhaps a 65Org32.

As for the hardware, $70 plus postage gets you 250k gates in a 40-pin module with 5v compatibility - for me that's £70 including postage and tax. OK, plus a programming cable. But for me that's a good price for (several iterations of) a homebrew CPU.

If we extend the 65816's multiplexed data/address bus idea, a 40-pin package breaks down to

2 vdd/vss
16 data (and address)
16 address (could also be data)
1 reset
1 read/write
2 nmi/irq (one or both could be optional)
1 clock out/ address latch enable - we use on-board clock source

leaving 1 pin free in the 40, plus the 9-pin test port topside.

If it's a 16-bit databus, and less than 32-bits of address, there are correspondingly more pins free.

The free pin or pins would give you one or more of

1 rdy - for wait states
1 be/aec - for bus sharing
1 set overflow - low latency input
1 abort - for virtual memory
1 ml - for shared memory
2 vpa / vda - for instruction set extensions
1 vp - for interrupt vectoring
1 m/x - 816-mode memory mapping control
1 E - 816-mode emulation state
1 chip select output - for a single peripheral chip
- could alternatively use highest address bits