I am wondering the best way to interface a 65xx device to the 68030?
I have the following circuit sketch:


Signal summary:
PH2 is a 14 MHz clock fed to the 6522.
XCS6522 is an active low chip select signal coming from a 68030 address bus decode.
DS is the 68030’s active low data strobe.
DSACK0 is a data transfer acknowledge for the ‘030.
CS6522 is the active low chip select fed to the 6522.

How it works:
If the data strobe is high, the circuit is held in the reset state and the 6522 not selected.
When the data strobe is low a negative edge on the PH2 clock will clock the XCS6522 signal through a DFF. This should drive the CS6522 low. On the next negative edge of the PH2 clock the data acknowledge DSACK0 will be activated. This will indicate to the ‘030 that the transfer is complete. At the same time the chip select to the 6522 is disabled. The circuit will remain in this state until the data strobe, DS, is de-asserted at which point the circuit will be reset.

_________________
http://www.finitron.ca

Two things about that circuit:

1. For a read cycle the 6522 stops outputting the data at the falling edge of PHI2. DSACK0 goes low shortly after that and the 68030 reads the data at some point after that (at the following falling edge of the 68030 clock?). I suppose parasitic capacitance will probably hold the data long enough provided the bus isn't too heavily loaded.
2. Is the PHI2 clock used for the VIA synchronous with the 68030 clock? If not, you will get occasional bad behaviour due to D and R inputs changing in the critical window around the rising edge of the 74AC74 clock input.

I was planning on using latches to hold the data, as in the following:

The pulse for the CAB clock is very short. A low on the select line SAB, SBA, causes data to be sent real-time. A high selects registered data.
The PHI2 clock is asynchronous to the '030 clock.
DS always follows XCS65xx timing wise. I need to work through the timing cases. I think if the FF's are reset in the timing window and the XCS6xx signal is not caught, it will be caught in the following clock cycle. The whole circuit delays until DSACK0 is asserted.

_________________
http://www.finitron.ca

Why don't you derive phi2 from the 68030 clock so it's synchronized?

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

That is a good thought, and the sensible thing to do. I have the processor clock being generated by a frequency synthesizer. I suppose I could divide it by four or possibly two. Assuming a 32+MHz CPU clock. I was using 14 MHz as a reference clock and feeding that to the 65xx circuitry. I guess an issue is timing via the 6522 counters would be affected. Can the counters count an external clock that is faster than the PHI2 clock?

_________________
http://www.finitron.ca

That is a fascinating question.... I was about to say yes until I thought maybe the (PB7?) input is synchronized before it gets to the counter ...
Then I thought use an external counter and read with the port eg PA but how do you ensure you don't get a value in the middle of counting, half old half new counter value...

You'd need a sampling frequency of twice (?) as high as your highest measurement, to latch the input signal, and that sampling frequency needs to be synchronized with the 6522 clock....right?

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

If you try reading something that is either high, low or something in between, you are only going to get alot of noise. You can’t securely determine wether its valid or not. Doubling the sampling frequency is not going to help since you don’t have anything to compare it with, so your sampling needs to be even higher than that. Doing things with two clock domains is.. interesting.. but I would not recommend it unless you have a very good reason. You also need to consider the transition time to be sure that you can determine the signal state.