Except the caveat about asserting RDY while Ø2 is low and possibly invalidating the bank address. I still think the safe route is to assert RDY when Ø2 goes high to avoid a timing glitch with the bank address.

In any case, in order to know when a wait state is needed, you'd have to know which device is being addressed, eh? You can't know that until A0-A15 are stable and the bank address has been latched and presented on A16-A23. By the time all that has occurred, Ø2 will be on the low-to-high transition, right? Therefore, you need to assert RDY after all that address stuff is done. Otherwise, how could you possibly know that the address points to something that requires a wait state?

This situation is analogous to what happens when you don't qualify write ops with Ø2. Since D0-D7 are not valid until approximately half way through Ø2 high (30ns in the case of a 14 MHz clock), failure to qualify RWB with Ø2 will randomly cause errors that only a logic analyzer would be likely to reveal. I see RDY as potentially posing the same sort of problem.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

It may be wishful thinking, but I think you don't need to. You need to have RDY stable and valid by the end of the cycle (less a setup time). You have the whole cycle (near enough) to do that, and it doesn't matter if RDY changes value several times beforehand.

This is the beauty of synchronous design: important things happen on clock edges - caused by them, or captured by them.

The difference between our positions is whether we think RDY is a synchronous or asynchronous input.

I don't think it's analogous to the problem of avoiding stray writes (which would happen if we allowed a write access to be seen by an asynchronous device before addresses are stable and decoded)

No difference. Although a design could treat RDY as an asynchronous input, it's clear that RDY is synchronous from the MPU's point of view, as it is sampled tPCS nanoseconds before the fall of Ø2 (that would be 10ns if Ø2 = 14 MHz). Similarly, RDY must remain asserted for tPCH nanoseconds (tPCH = 10 if Ø2 = 14 MHz) after the fall of Ø2 in order for the MPU to halt. Assuming these timing requirements are met, the MPU will maintain bus state indefinitely until RDY goes high.

My position is that it's improper design to assert RDY while Ø2 is low. The need for a wait state can only be known when Ø2 goes high, at which time a valid address will be present. Therefore, if the addressed device is slower than a normal bus cycle, RDY would have to be asserted immediately on the rise of Ø2, but well before Ø2 goes low again. Otherwise, the MPU will not see the state of RDY at the right time and will not halt in time to accommodate the slow device.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!