Over on http://forum.6502.org/viewtopic.php?f=1&t=7223 I asked the question of what if the 6502 were extended to a 24-bit address bus, followed by other major architectural additions.

Then this week I discovered the 6507, the Atari 2600 variation of the 6502 that drops 3 bits of address bus and interrupts, but which in reality is just a 6502 with IRQ and NMI tied to 5V and the top 3 address bits unconnected to pins. That made me wonder how many transistors could be saved if the 6502 were actually pared down.

Thanks to @Arlet and all my past adventures with his 95% complete Verilog 65C02, this was a very simple question to answer. The result is the https://github.com/lunarmobiscuit/verilog-65CFF-fsm, which is little more than Arlet's code with a lot of `ifdef's to turn off various features.

Synthesize with -D AB13 and you don't just get a 13-bit address bus, you get a 65CFF that only has 13 bits in its PC register. Or use -D AB14 if you prefer accessing 16K to 8K with 14-bits. Don't specify a width and you get the original 16-bits.

But with this code you have to specify -D STACK if you want an S register, and PHx, PLx, TSX, TXS, JSR, and RTS opcodes. Specify -D IRQ or there is no CLI, SEI, or RTI opcodes, and no logic to set the I flag (which I left as there is such a thing as too many `ifdefs).

Synthesize -D AB13 -D STACK and you have the 6507 functionality but with only the logic required for that chip (with the one exception that the stack is still in page one instead of page zero).

Beyond the anachronistic Atari 2600, why would anyone want this design? Here in the 21st Century, optimizing away 100 transistors is a waste of time and testing. But I wanted to see how easily it could be done (in Verilog), and to see the netlists shrink as the capabilities were culled. They do, but not significantly.

After diving into how the 2600 worked, I was once again pondering what Woz would have done if Apple had purchased MOS or Synertek. Woz with a chip design team and fab would have been able to mix a minimal 6502 core with his Woz Machine floppy logic for a 2-3 chip standalone floppy controller. Or a minimal 6502 core plus the graphics side of the Apple ][ board for a 2-3 chip graphics processor. Atari probably could have fit their TIA into the 6502 die if they could have culled out BCD, all the extra opcodes, and the extra flip flops from PC.

Yet more alternative universe possibilities.

(And if you didn't see the joke in the name, it's 65CFF, with FF as in negative 02, as in the "65 negative 2").

Oops... lack of sleep... it was supposed to be the 65CFE. Joke is apparently on me.

In terms of a programming model does this CPU treat the top bits of a 16 bit address as don't care?

For example, suppose I use a page zero indirect addressing mode. There are two bytes in the address, but your address space is smaller. Also on reset I assume the vectors are at the top of this smaller address space.

My guess is that he reduced the address register to 13 bits. Thus bits 14 & 15 of the address line doesn’t exist. Still, the cpu will have to read the MSB of the address to fetch bit 8-13, so in that regard it does read them before discarding bit 14 & 15. At least that is how I read it..

Yes. The AB register doesn’t store those upper bits nor would there be any matching address bus pins.

So for a 13-bit address bus $1000 = $3000 = $5000 = $7000 = … $F000.

Which, BTW, means that the vectors move down as well, without actually changing the hard-wired valued of $FFFx in the CPU.

Instead of all the ifdef's you could try just having a defined constant for upper address bit in the top module. The synthesis tool should then optimize away all unused intermediate signals.

Thanks. I speak Verilog only a little better than I speak bocce.