At long last I have received PCBs for the 2nd iteration of my SBC: the n8 Bit Special. The n8 Bit Special is an open-source 65C02 SBC with core functionality on a 100x100mm 4-layer PCB and 3 ports for small and focused expansion cards. Hardware information, PCBs, GAL code, etc. can be found here on github.

Some notable elements of this design are:

• centered around a 65C02 in a PLCC package
• built-in SC28L92 DUART for timing and serial connection
• a USB micro port connected to a CH340X USB-to-serial SOP so it can be directly connected to and powered by another computer
• glue logic is handled by an ATF22V10 so address space and memory topography is configurable
• 48k RAM and 16k ROM (though as stated above, this is completely configurable!)
• runs at 3,6864 Mhz (eventually. ROM code still uses an R65C51 that maxes out at 2 Mhz so while I bootstrap 28L92 drivers, it runs at half that, 1,8432 Mhz)
• 3 n8 Bus expansion ports (definition, template PCBS, and more of this "standard" is provided on github)

I posted the schematic (buried deep) on another post but at that time it wasn't tested. Now it is!

Right now it's basically running the ROM from v1 of the board with very few changes and has a VIA and ACIA in expansion slots. Will post real-life photos on a 2nd post

As promised here are some real-world photos of the n8 Bit Special in action! My first test was a free-run test. I hardcoded $EA on the databus and observed the low 6 address bits from an expansion port. A very complicated clock divider!

Next I hooked up RAM (x2), ROM, a VIA and an ACIA. It's running an old version of the ROM that isn't SC28L92 aware. Here i have both the ACIA and SC28L92 hooked up to my computer so I can bootstrap an SC28L92 driver.

Hi Nate,

Congrats on the SBC V2... looks nice... tidy layout. A few things to note:

- It would have been more flexible to have separate the clocks for the CPU and the SC28L92.
- Looking at your WinCUPL config, you shouldn't qualify RAM selects with Ph2 of the clock, only the Read/Write lines, which you did. It might create some odd timings and put things on the edge.
- If you were to just connect A15 to the /CS line of the lower RAM, you could free up a line on the 22V10 and generate the Read and Write signals for ROM/RAM, I/O without the 74HC00.

Of course, the last comment states that the first 32KB will always be RAM.

Lastly, feel free to look at my GitHub page... I have BIOS code that configures and runs the SC28L92 for both serial ports and the counter/timer used as a jiffy clock.

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Regards, KM
https://github.com/floobydust

Yes it would, but one of my major goals was to just make it as compact as possible to get that sweet JCB PCB price point, $8 for 5 4-layer boards as of this writing. In the future, if things go well, I can double the clock to 7,something (not going to do the math right now ) and just change some DUART settings


I no longer qualify them on the GAL. I need to upload my latest (there are some changes made to GAL and ROM that aren't reflected in the repo right now)


This is an intriguing idea for the future. I did pipe CLK and R~W into the GAL for these exact kinds of reasons. Will play with this but maybe in a month or two. The high of a working new design hasn't worn off yet.


I will do this. I am running into trouble where interrupts aren't firing!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

It turns out the interrupts weren't firing because I was writing to $05 (the IMR offset) instead of DUART_BASE+$05 All cleared up now. So far no problems running both the system and 28L92 from same 3,6Mhz main clock source.

I also pushed actual GAL PLD code which does not qualify CLK with any CS signals.