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 Post subject: PCF8584
PostPosted: Tue Jul 19, 2022 2:00 am 
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Has anyone successfully interfaced a PCF8584 I2C bus controller to a 6502?

I just can't seem to get it to work directly on the 6502 bus.

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 11:45 am 
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I haven't yet, so unfortunately I can't help you. But I got some to try a while ago and will be following this thread!

When you say "directly", do you mean it worked before when hooked up to a VIA or something? If so I suspect timing issues maybe?

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 12:26 pm 
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Damn i wish i would've known of this thing before i placed my mouser order, i could've made a small expansion card for one of my SBCs to test it out. (sadly the DIP version is not being sold anymore)
The timings appear to be compatible with a 65xx CPU in either 80xx or 68k Mode. (only real different that in 68k mode R/W are combined and 80xx mode has them as seperate RD and WR signals)...
so it should be working assuming that you pull RD/WR low atleast 10ns before pulling CS low (for reading, and opposite for writing). and that you also wait ~150ns before pulling RD/WR or CS back high.

and i do like the fact that it's comaptible with the 8088 as well, so in theory you could put this on an ISA Card and would only need a DOS Driver to make I2C usable on an IBM PC.


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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 12:47 pm 
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akohlbecker wrote:
I haven't yet, so unfortunately I can't help you. But I got some to try a while ago and will be following this thread!

When you say "directly", do you mean it worked before when hooked up to a VIA or something? If so I suspect timing issues maybe?


I haven't tried it through a VIA yet but I'm guessing you would be able to use it that way in either mode.

I think the problem is the mode switching. It's not explicitly stated in the data sheet, but I think the /WR and /CE are more critical than /WR sometime before /CE. I think they really mean /CE must be asserted after but while /WR is still asserted. With the 6502 you would need to initialize the PCF8584 before you wrote anything anywhere else. It seems to just lock up and not work in either mode and I think that is because if it's exposed to the /WR signal being asserted without the /CE following immediately and while /WR is still asserted it just gets confused. They hint at this when they say the /WR and /CE must be kept stable after a system reset.

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 2:47 pm 
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It does seem a bit murky. And I'm puzzling over the following sentence from Section 6.2 regarding the mode initialization that automatically occurs at startup:
Quote:
If a HIGH-to-LOW transition of WR (R/W) is detected while CS is HIGH, the 68000-type interface mode is selected

And 68000 mode is what we want (I guess). And, the sentence seems to say that CS needs to be high when R/W falls. So, does that mean that CS needs to be qualified with Phi2? Maybe it's worth trying it that way, if you haven't already. (You haven't shared your schematic.)

BTW, here's the datasheet, for anyone who hasn't seen it yet.

-- Jeff


Attachments:
PCF8584.pdf [180.27 KiB]
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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 3:21 pm 
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hey Jeff, I didn't draw up a schematic, but it was trivial.

The device connected straight to the data and address bus with /WR and /CS being fed from a gal. The gal did the decode and also had Phi2 and W/R feeding it so that I could try either method. I was most interested in the 68000 mode and used a scope on /DTACK to see if it got asserted, which my reading of the datasheet tells me it should be asserted once 68000 mode is entered. Yes, I did qualify /CE with Phi2. No luck.

Of course, it could be a dead chip, but I do have 2 of them and neither gave me the result I expected. They could also both be phonies as I got them from eBay. Unfortunately I was not able to find the PDIP version anywhere else at the time.

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 3:36 pm 
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BillO wrote:
Yes, I did qualify /CE with Phi2. No luck.
And during this test the PCF8584's R/W input was simply seeing a copy of the CPU's R/W signal, is that right? Just checking.

Maybe your path of least resistance is to give up on 68xxx mode and shoot for 80xx mode instead (which is mentioned as the default for the PCF8584). Since you have the GAL there, perhaps it wouldn't take much to generate separate /RD and /WR strobes.

-- Jeff

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 3:46 pm 
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Yes. W/R without qualifying.

I could try the 80XX mode I guess. The computers I'm trying it on both create qualified /WR and /RD signals anyway..

I want to set up a test jig for testing random ICs for those computers anyway. The PCF8584 can be my first test case.

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 5:01 pm 
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I have DIP version of PCF8584 and tested it on a RC2014 prototype board (Z80 timing). I had it talked successfully to a serial EEPROM (AT24C256). My problem with PCF8584 is it is too slow--100Kb/s max. 14MHz 6502 can bit bang I2C faster than PCF8584. I bit-bang BadApple! video to I2C 128x64 OLED display at the rate of 31mS per 1K image which is 300Kb/s data rate.
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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 5:55 pm 
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See here http://www.6502.org/users/andre/csa/scsi/index.html

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 7:18 pm 
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fachat wrote:


Thanks Andre. I notice though the you tie pin 16 to Vcc. According to the datasheet that becomes the /DTACK output in 68K mode with an open drain. Things are working okay that way? I'm guessing 2K-4K7 resistor might be a better choice??

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 8:03 pm 
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BillO wrote:
fachat wrote:


Thanks Andre. I notice though the you tie pin 16 to Vcc. According to the datasheet that becomes the /DTACK output in 68K mode with an open drain. Things are working okay that way? I'm guessing 2K-4K7 resistor might be a better choice??


Hm, if that is so, probably a good idea :-)

Haven't really tested it that hard I have to admit. Never really found a good use case for i2c as opposed to more accessible spi.

André

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 Post subject: Re: PCF8584
PostPosted: Tue Jul 19, 2022 9:13 pm 
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fachat wrote:
Never really found a good use case for i2c as opposed to more accessible spi.

I²C is very common for things that don't need the speed of SPI and where you might benefit from reducing the number of connections compared to what SPI needs. Typical examples are:

  • realtime clock (time of day and calendar, with alarms, with resolution of 10ms or 100ms or even 1s)
  • small EEPROM memories for storing default setups, particularly the 24xx series which ranges from 16 bytes up to 128KB, but not megabytes
  • keypad scanners
  • touch-screen controllers
  • relay drivers
  • LED display drivers
  • power sensors
  • temperature sensors
  • thermal management
  • digital pots
  • programmable oscillators
  • power supply control
  • data converters that don't need audio or video sampling speeds

I would venture to say there are thousands of I²C ICs on the market.

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 Post subject: Re: PCF8584
PostPosted: Wed Jul 20, 2022 6:07 pm 
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I knew someone would chime in ;-)

As a hobbyist 15 years ago with prices of 10+€ for a single controller and general high prices compared to simple TTL shift registers there was just no motivation for me. I even added the two lines on my bus backplane, but never really used it.

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 Post subject: Re: PCF8584
PostPosted: Fri Jul 29, 2022 6:31 am 
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Here are some advantages to I²C, copy-and-pasted from something I recently emailed a friend:

  • You don't need a separate select pin for each device connected to the I²C bus.

  • I²C also allows passing control around (although I've never had a need for that).

  • I have never seen an I²C device that couldn't handle 5V. AFAIK, they all can do 5V, which makes sense when you think about the fact that since they won't be huge memories that use tens of millions of transistors, they don't need the smaller die feature sizes that max out at 3.3V or lower; and since passive pull-ups along with the parasitic bus capacitance limit the bus speed, they also don't need the higher speeds that tend to go with smaller die-feature sizes.

  • Many I²C devices can dictate their data rate by holding the clock line down if they need more time to process each bit. The controller watches for the clock line to be up before pulling it back down; so it won't get ahead of the device.

  • I²C doesn't have the different modes like SPI does. It's all just one mode, making it simpler.

I like both I²C and SPI, for different reasons and applications. I just added a tiny I2C-6 32Kx8 I²C EEPROM module to the front page of my site. There's a link to the data sheet there too.

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