hmm, that is interesting. so far every circuit i made for the ATF1508 with Quartus and POF2JED has worked perfectly fine.
maybe there is just something specific about your circuit that either Quartus or POF2JED is having issues with.

on a different note, i just noticed that because the SRAM is SMT i could in theory put one of the chips on the front of the PCB and the other below it on the backside, effectively halving the space required.
i already mirrored the address/data lines for one of the chips so placing them ontop of eachother should only have minimal crossings (besides the vias required to connect the bottom/top sides of the PCB of course)

Even without one of the SRAM ICs on the backside the whole thing still somehow fits into 10x10cm. but it is getting very tight.

Top right is the Power circuit, top left is the USB and PS2 stuff, bottom left is the clock circuit and Oscillator, and bottom middle/right has some buttons and the JTAG Header for the CPLD.
Middle has the expansion connector with the CPLD on the right (with RAM right below it) and the CPU, VIA, and ROM on the left.



I'm not sure if this is possible to route though, i'll have to see.

I also need to reassign some pins on the Expansion Connector, as currently all the clock signals are near the top of the connector while the clock circuit is in the bottom left, so i'll move those pins closer to the circuit to hopefully keep the clock a bit cleaner.

And finally I gave up with the 3 spare PB pins i had from the VIA and just threw them on a small header. i doubt i'll use them for any expansion but i can imagine them being useful for debugging stuff with an Oscilloscope or logic probe.

thoughts on this layout?

Autoroutes should be able to route the board given fine pitch design rules like 6 mil trace and 6 mil spacing.

I’m interested in building your board. Shipping from Germany to USA is probably too expensive so I can order the pcb myself if you’ll release the artwork and schematics.
Bill

I can throw the entire Kicad folder including the CPLD Logic (and a simple USB Bootloader) onto Github once the whole thing is done, ordered, assembled, and tested.

Freerouting (an Autorouter) has been sitting in the background of my PC for like +3 hours and it's currently trying to optimize away the vias, of which there currently are ~190 (it started at like 300).

Wow autorouters have come a long way. I'd have expected for that layout to not even be routable due to the use of PLCC (that I find more difficult to route) and the general density.

Is this a 2 or 4 layer board?

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

i had to change some settings to make the autorouter less afraid of using vias so that it would route this at all, but afterwards it optimized away a pretty big chunk of them.

it is a 4 layer PCB, with the 2 inner layers used for 5V and GND. here a screenshot of it with only the top/bottom layers shown

(and yes there is a smiley on the back silkscreen where the CPU socket is, because why not?)

I am basically ready to order the PCBs, which is both exciting and scary as any mistakes found after ordering them will hurt way more.
but i also kinda want to say "screw it", order them, and then just deal with the potential issues when i have it in my hands.

There are guides that actually advice against vcc and gnd as inner layers in a 4 layer board and use two gnd inner layers instead. It may work, I'm running 12.5MHz on a two layer board even...

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

i'll just have to try and see, my previous 65C02 SBC ran up to 20MHz on a 2 layer board.
i'm only really using 4 layers because someone suggested it.
And because it's cheap enough and i never tried it, i thought why not?


That is very intersting, i had no idea they had different gaps between the copper layers, i thought all of them were the same distance from eachother. and your Numbers are pretty spot on for what JLC says. 0.21mm between layer 1 & 2 and layer 3 & 4, and 1.065mm between layer 2 & 3.


hmm, with a target speed of 25MHz would that cause an issue here? and if i were to use 2 GND layers, then what about Vcc? it would need to be routed on the top/bottom layers like the signal lines, wouldn't that also cause problems with signals using it as a return path?
or this is more of a thing for much higher speed circuits like +100MHz and FPGAs and such?

The good thing about the 6502 is, about the only high speed signal where transitions really matter is phi2. You can have Ax ring before phi2 high, as long as it -and derived select lines - are stable during phi2 high, everything's fine... similarly for the data lines at the end of phi2. (... duck and cover )

Edit: at least that is I think why we still get good results even with crappy board designs (explicitly including mine)

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

16Mhz '816 on a two layer board here ...

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

The problem is not the clock frequency but the higher frequencies caused by the transitions. 25MHz can easily translate to 100s of MHz with fast logic with high switching speeds

My take is with two ground layers in between signals would try to use these as return path instead of the power on the same plane.
But if I understand it right, the two gnd planes would have to be coupled with lots of gnd vias to provide return paths for the signals crossing them

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

While W65C02 is 1970 computer technology, it is built with 0.6um process which was cutting edge technology in 1995 (75-120MHz Pentium released in Oct 1994 was based on 0.6um process). So yes, W65C02 is capable of very fast edge like a 100MHz part. Having said that, your design has dedicated power/ground planes, it is small 100mmX100mm, and you are using PLCC packages. Considering many of us had successfully experimented with DIP W65C02 on solderless proto board or large 2-layer PC board while running clock to mid-20MHz, your design have so many safety margins that I really don't think you should worry about it. Your layout picture looks good, you are good to go!
Bill

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x86?  We ain't got no x86.  We don't NEED no stinking x86!