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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

What kind of speed are you looking for?

You could use 14 1N4009 diodes and an FMMT2369 transistor to build a 3ns-4ns 14 input NOR gate. Should be dead easy to source these

You get it down to under 2ns if you used MAU2D3000B schottky diodes or even quicker if you wanted to look hard. But I get the impression most of the 6502.org folks are not much into experimentation of any kind.

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Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Any reason not to use a CPLD? Seems to me an ideal solution for glue logic, unless cost is an overriding concern, or you want to use up stocks of 74-series.

(I was briefly excited by the diodes idea too! From diode logic to CPLD - that's a journey of more than half a century.)

If you really need a huge IO space, then skip the rest of the response, but if there are a bank of IO locations that would be heavily used, it seems easy enough to allow the top of lower half of the 64kB bank (or some smaller chunk to "bleed" into each bank. Flip a bit for bleeding, use the IO, and then flip it out.

Jim

They are maximums when driven deep into saturation at 3V. With proper bias you should be able to achieve substantially better response as well as using a totem pole output to deal with driving the capacitance, but I see where you're going.

Even with a couple of ACT gates in line you're looking at 9 or more ns.

What about a combination of Schottky diodes and one ACT gate? You might get close to 6ns.

You might also be able to alleviate some of the capacitive load on the data and address busses by using BS62LV1605 2Mx8 sram. They are a 5v version of the 3.6v part I’ve used before.

7ns. You’re pushing this technology pretty far. I think you are running this architecture to its limit. Next step for you will be a two-stage memory architecture using a small synchronous block of memory at the processor speed then a larger asynchronous store for ROM, the rest of RAM and I/O. That might be a complicated proposition with the 65Cxxx family though.

_________________
Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

For 16V8 and 22V10 GAL's, the cost would be about $ 45-75 for a programmer from my favorite store (Ebay). You can download WINCUPL from Atmel for free (registration required IIRC).

The download includes some sample logic and it was easy to pick up. I designed a decoder for a Commdore PET using one 16V8. A few years back, I designed a simple SBC aimed at beginners (6502-32k ram - 32k rom - 65c22 - 65c51) using one 22v10. I did not complete the project but do have the CUPL files that I would be glad to share.

For the Xilinx XC9572 (65SPI) and XC95108 (SBC-3) CPLD's, I got lucky on Ebay and got a parallel port JTAG programmer for $25. Xilinx also has free software to compile your logic into the necessary JED files and the programming software is built-in.

Now that I am where I am with these, I cannot imagine going back to 74 series for address decoding. I can point you in the right direction for the programming hardware if you are interested.

Daryl

Sorry for missing (or forgetting) your earlier position statement.

We're using xilinx xc9572 at 5v. The plcc44 10ns part is $7.50 at digikey, or an xc9536 at 7.5ns is $5. The Xilinx software is zero cost and runs fine on linux, optionally from command line.

Describing a combinational circuit in verilog isn't so different from writing equations.

I think a parallel-port programming cable can be made up from spare parts although we got one thrown in with a breakout board from MCUMall (presently out of stock)

Yes, it's overkill for a single gate - although that isn't in itself a disqualifier - but if you can also include the address latch and some other glue, it looks better value. We went for a plcc84 part to be sure to have the pin count to soak up all the glue.

They are also relatively slow: 55ns being typical. I think the SRAMs that Garth is planning on using are in the 10-15ns range. Complicating matters is the BS62LV1605 is available in TSOP2 or BGA packages, but not something more hobby-friendly like SOJ.


It may be. However, I'm surmising Garth is probably looking at the cumulative gate delay that will sabotage timing when he cranks up the MPU clock. As the '816 can run at 20 MHz (Vcc = 5), that leaves less than 25ns for memory decoding and selection to stabilize. So his desire to get into the single digit nanosecond range is completely understandable. I'm trying to head in that direction as well in a design i am concocting, although I think I'll turn to a CPLD when I get to that point. 74AC' logic can only go so fast...

BTW, who sells a 1N4009? I couldn't find it on any of my usual sources.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Don't know off hand. I've got a couple still lying around along with other 1N400x diodes. I usually buy stuff from Actvie Components, Future Electronics or Sayal if I can't get it on eBay. Could have been from any of them.

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Bill