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BigDumbDinosaur
 Post subject: Re: Bus termination...
PostPosted: Sun Jun 05, 2022 7:24 am 
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fredericsegard wrote:
I'm in the process of designing a backplane...One of the inner layers is a VCC plane, and the other is a ground plane (or should they be both ground planes?).

I recommend you make one plane the ground and the other VCC. If you don’t have to distribute VCC via traces to the sockets you can gain some density in your layout.

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Front and back layers are also ground copper-filled.

That I don’t recommend. All you are doing is adding unwanted parasitic capacitance to the board. The only place I’d use outer layer filled planes would be around the power input socket and associated components to assist in keeping EMI from back-feeding to the power source.

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I'm wondering if it will be pertinent to implement bus termination (in part because it's a relatively short bus).

That gets into some sticky design decisions. In looking at your schematic, I am not getting a sense of what will be driving the buses, which is kind of important. Bus termination is something with which you will likely have to experiment. You’ve got two considerations: reflections and ringing. The former are provoked by impedance mismatch and the latter is provoked by impedance mismatch and fast edges, the latter which are characteristic of the 74ABT and 74AC(T) logic families.

There are several impedance-matching techniques you can use, the simplest being Thévenin termination, for which resistor packs are available. Thévenin termination has used on parallel SCSI buses, where it has proved to be workable up to around 10 MHz. This link has an article on various termination techniques, including Thévenin. Thévenin termination, however, will have only moderate effect on ringing induced by fast edges.

Another method is called “perfect termination,” which is a little more involved, using both diodes and resistors. The diodes’ primary role is to suppress over- and undershoot that arises from ringing. Diodes alone won't do anything about impedance mismatch, which is where the resistors get into the picture. However...

On buses with unknown characteristic impedance, Schottky diode arrays have proved to be workable. Basically, two diodes are connected in series, with the anode of one diode grounded and the cathode of the other diode connected to VCC. The junction of the diodes is connected to the signal line. The diodes have to be very fast to do any good.

Speaking of ringing, it isn’t necessarily a problem if the voltage excursions do not go into the receiving device’s input "no man’s land." This can be readily determine with a good scope equipped with a compensated probe on the ×10 setting. If the excursions solidly stay in CMOS logic 0 or logic 1 territory, ringing should not result in an unstable circuit.

All that said, unless you have a reasonably good idea as to the bus’ characteristic impedance, you could end up worse off with termination.

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I plan on running my bus at 8HMz. If all my signals are properly driven with ABT family of chips, should I still consider termination?

See above. Also, I don't recommend 74ABT in this application. 74ABT produces TTL-level outputs, not CMOS. 74AC would be my choice, assuming proper ringing suppression is present (there are Schottky diode arrays for that purpose). 74AHC is similar in performance to 74AC—propagation times are about the same—but with less aggressive outputs.

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Do all signals benefit from termination?

Not “slow” signals such as reset.

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What seems to be popular is the resistor divider 330Ω-220Ω termination scheme.

That would be used with Thévenin termination.

Quote:
There's also the 2.85 V regulator with 220Ω series resistors to the signals may also be an option.

Active termination in this application is, in my opinion, overkill. You won’t be running fast enough to get any value from it.

Ultimately, the choice of termination is one of trial-and-error in a new design. Theory will only get you so far.

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What about normally pulled-up lines like /IRQ, /NMI, BE, etc?

These you have to be careful with, especially /IRQ. Anything that slows down /IRQ will open the door to spurious interrupts, which will likely make your system unstable and will drive you crazy. I would not wire-OR /IRQ and /NMI on a backplane. Each interrupting source should be wired to the input of an AND gate and the gate’s output used to drive /IRQ and /NMI. Since you have eight slots and since an eight-input AND in fast logic is not a stock item, you can use an eight-input NAND, such as a 74AHC30 and invert its output. The inverted output would be wired to /IRQ, which will be driven high as well as low—no pullup resistor needed. A similar arrangement could be used with /NMI.

I don’t want to sound discouraging, but designing a workable backplane arrangement is not in the least trivial. Aside from possible transmission line issues involved with long signal traces, there’s parasitic capacitance that can distort signals and interfere with reliable operation. Most bus systems deal with parasitic capacitance by using a buffer-driver or a transceiver for bi-directional circuits. Signal skew can also be a potential problem, although at 8 MHz, unlikely.

I’d think very carefully about what you are trying to accomplish before committing to this route.

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fredericsegard
 Post subject: Re: Bus termination...
PostPosted: Sun Jun 05, 2022 12:29 pm 
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GARTHWILSON wrote:
See the 6502 primer's page about construction for good AC performance, at http://wilsonminesco.com/6502primer/construction.html . It has good links to lectures and articles about termination; but I also just expanded it to cover the matter of connector pinout, since you only have power and ground at the ends, something that is ok only for slow components.

That was a good read. Here is what I gathered so far that applies to my board since I plan to go well above the 1MHz barrier:
- Ditch the breadboard header
- Put more ground and power at the connector level so no signal pin is more than 0.2" away.
- Must be a 4-layer board with the proper ground and power planes
- Make sure power and ground are well routed.

Question: should I use the inner ground and power layers to distribute power to the connectors, or should I use the outer layers for that, or both? Alternatively, if I do a 2-layer board and route everything on a single layer, could the other layer be the ground layer.

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fredericsegard
 Post subject: Re: Bus termination...
PostPosted: Sun Jun 05, 2022 12:46 pm 
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BigDumbDinosaur wrote:
I’d think very carefully about what you are trying to accomplish before committing to this route.

This is why I'm taking my time to research the subject. Thank you for your answers, it highlights a lot of things I need to take into consideration.

About termination, if there are none at the backplane board level, could termination be done via an add-on card at the end of the line? That is if there is a need for it.

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BigDumbDinosaur
 Post subject: Re: Bus termination...
PostPosted: Mon Jun 06, 2022 1:46 am 
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fredericsegard wrote:
Question: should I use the inner ground and power layers to distribute power to the connectors...

Yes. With internal power and ground layers, there is no good reason to use traces for VCC and ground. In fact, doing so will likely make the board noisier.

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Alternatively, if I do a 2-layer board...

That I wouldn’t do.

The cost of having four-layer boards made has plummeted in recent years. In my opinion, there is absolutely no good reason to use a two-layer board with digital electronics, unless using slow logic on a unit where density isn’t a concern.

Keep in mind that at the speeds we run in our systems, it isn’t the operating frequency that causes the onerous problems. It is the abrupt rise and fall of signals. The WDC MPUs generate very fast edges, which equate to effective frequencies in the hundreds of megahertz range during switching. 74AC and 74AHC logic also produces fast edges—74AHC less so. 74HC has about the same output characteristics as 74AHC, but with slower propagation.

My point is you are designing for the effective frequency of those edges, not the Ø2 frequency. This is where a multi-layer board with power and ground layers is a big help.

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About termination, if there are none at the backplane board level, could termination be done via an add-on card at the end of the line? That is if there is a need for it.

That I can't definitively answer. It would depend on which type of termination you would use. However...

Since your backplane is a bus with multiple stubs (the sockets and the cards plugged into them), ideally it would be terminated at both ends to match the characteristic impedance of the bus, which is an unknown. All high-speed buses I've seen place the termination at the bus ends, not the stubs. Given the unknowns in your design, I'm inclined to recommend Schottky arrays, one at each end. They should be on the backplane board and should be the last thing attached to the bus at each end. On the cards, keep signal paths short to minimize impedance mismatch reflections.

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fredericsegard
 Post subject: Re: Bus termination...
PostPosted: Mon Jun 06, 2022 2:38 am 
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BigDumbDinosaur wrote:
Since your backplane is a bus with multiple stubs (the sockets and the cards plugged into them), ideally it would be terminated at both ends to match the characteristic impedance of the bus, which is an unknown. All high-speed buses I've seen place the termination at the bus ends, not the stubs. Given the unknowns in your design, I'm inclined to recommend Schottky arrays, one at each end. They should be on the backplane board and should be the last thing attached to the bus at each end. On the cards, keep signal paths short to minimize impedance mismatch reflections.

All signals benefit from termination? (with the exception of /reset maybe?)

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BigDumbDinosaur
 Post subject: Re: Bus termination...
PostPosted: Mon Jun 06, 2022 5:52 am 
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fredericsegard wrote:
All signals benefit from termination? (with the exception of /reset maybe?)

Theoretically, yes. In reality, it depends... :D

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fredericsegard
 Post subject: Re: Bus termination...
PostPosted: Mon Jun 06, 2022 10:37 am 
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BigDumbDinosaur wrote:
Theoretically, yes. In reality, it depends... :D
:lol: :lol: :lol:

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BigEd
 Post subject: Re: Bus termination...
PostPosted: Mon Jun 06, 2022 12:02 pm 
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I think if you look at the length of the signal run and the length of any offshoots, and look at the speed of light, you get an idea of the timescale of the reflection problem. I'm pretty sure that a few inches, at our typical frequencies and edge rates, is not significant.
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BigDumbDinosaur
 Post subject: Re: Bus termination...
PostPosted: Mon Jun 06, 2022 5:15 pm 
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BigEd wrote:
I think if you look at the length of the signal run and the length of any offshoots, and look at the speed of light, you get an idea of the timescale of the reflection problem. I'm pretty sure that a few inches, at our typical frequencies and edge rates, is not significant.

On my POC V1.2 unit, some of the address bus runs and all of the data bus runs extend approximately five inches as the crow flies. That unit easily runs at 20 MHz. Although a given Ø2 rate alone doesn't determine if a design will go or blow, as Ø2 is ramped up, less time will exist for bus states to settle following a transition. Ergo instability will definitely arise if that bus settle time is insufficient.

That said, Frederic’s situation is a little different because the bus driver could be any one of the slots. Theoretically, that could give rise to significant reflection problems if the bus is not terminated. What I would do would be to make provisions in the board layout to accept termination, but try running without it. Assuming a high-bandwidth scope is available, it should be readily apparent if termination is needed.

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BigEd
 Post subject: Re: Bus termination...
PostPosted: Mon Jun 06, 2022 5:23 pm 
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It's true that the situation will be more complex, but the various reflections still only have some distance to travel.

As noted before and elsewhere, it's clocks and strobes which are most vulnerable to having their edges corrupted or replicated. Ordinary signals merely need to be stable by some critical time (and stable until some critical time.)
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BigDumbDinosaur
 Post subject: Re: Bus termination...
PostPosted: Mon Jun 06, 2022 5:33 pm 
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BigEd wrote:
...Ordinary signals merely need to be stable by some critical time (and stable until some critical time.)

Which is why I’d first try it out with no termination. It may prove to be a non-issue.

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Sheep64
 Post subject: Re: Bus termination...
PostPosted: Sat Jul 09, 2022 4:19 pm 
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The problem with four layer card systems is that signals have a continuous ground plane - except when they cross from card to backplane and back again.

Anyone who has configured SCSI will know that you can probably omit bus termination if you have one host and one device. That's a point-to-point connection and current takes a direct route. Signal reflection gets really bad when current has opportunity to branch. Thankfully, you don't have the speed or distance which causes 100Mb/s Ethernet packets to interfere through each other like ripples on a pond. In this case, the intended recipient may miss both packets unless another node forces resend. Regardless, you are likely to have a card system where two cards don't require termination. Three cards may not require termination; especially if a processor card is at one end. However, an arbitrary arrangement of cards may fail without termination.

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