Interesting. If I pull the CMOS chip so that the 74LSxx chip is just driving the scope and the empty circuitry, the dip goes away.

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Bill

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Pulling the chip reduces the capacitance being driven by just under half.

I'll see if a small amount of resistive loading changes things, but that will have to wait for tomorrow.

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Bill

CMOS logic has a current spike right at the threshold point as both P and N channel conducting. This is why you can't let CMOS input float--it'll goes to threshold point and draw lots of current. That current spike may feed back to the ground of probe.
Bill

I could test that by not powering up the CMOS chip. Just bend the Vdd lead out of the socket.

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Bill

The effective input capacitance will be increased by the miller effect when the input voltage is close to the threshold. Far from the threshold the input capacitance will be Cgs + Cgd, but around the threshold it will be Cgs + Cgd * (1 + G) where G is the stage gain (rate of change of drain voltage with gate voltage).

Do you also have a circuit-level electrolytic at the point where power is brought into the circuit?

That dip certainly sounds to me like an effect of the clock itself: it's causing something major to happen. Which is the point. But it shouldn't feed back to the clock signal. I rather suspect it's the power and ground that's the cause - or, equally, perhaps it is a measurement artefact.

Indeed I do. There is a 100uF electrolytic with an ESR of 0.03 ohms. In fact, the power is applied through it leads.


So here a some scope images of the event. As a note, I also tried a scope probe from a different manufacturer and the results were exactly the same.

This with the just 6 CMOS loads:
Note how the voltage rises slowly after the rigning settles down.


This is with the 6 CMOS loads and a 10K resistor:
The rise time and dip are the same, but the voltage does not increase after the ringing settles down.


This is with 6 LS TTL loads:
The rise time is a tad slower, but the dip is much reduced. The voltage reached (3.7V) is not as high as with the CMOS loads, but we do get the slow rise. Note that we can no longer reach 0V. It looks like about 0.05V at the lowest.


This is with 6 TTL loads:
Rise time to 3.5V is quite a bit slower (3-4ns). The dip is not as bad as the CMOS loads but worse than the LS TTL loads. We reach the same 3.7V as with the LS loads but we don't get the slow increase. Low voltage has increased to 0.15V


This is with the 6 CMOS loads but the power (Vdd) removed from the CMOS IC:
This is strange and unexpected. The dip is gone, but the maximum voltage reached is reduced to 3.6V and the time to reach 3.5V has increased by 10ns!? There is no slow rise.


And this is with no IC, just the circuitry load (~12pF):
Again no dip and rise time is increased over having a device load.


I am more confused than ever now.

_________________
Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Just a thought Bill, perhaps if you show some photos of your circuit and your probing, there might be observations to be made.

The reduced output voltage with power removed from the chip could be due to loading of the input via the protection diode.

I'll do that tomorrow.

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Bill

Garth mentioned this too. Could be, and you definitely see a non-linearity as the voltage rises. However how do we explain the reduced voltage and slow rise time when there is no chip at all?

_________________
Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Conventional current flow is the only way to go, if the aim is to communicate. (Unless you're discussing Hall effect sensors or cathode ray tubes...)

Why those annotations don't use the letter I, that would be my question. Surely these are currents?