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BigDumbDinosaur
PostPosted: Fri Jul 08, 2022 3:55 pm 
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Proxy wrote:
alright i've opted to just use BDD's Clock circuit from his POC v1.3 instead of Dr Jefyll's circuit...but one thing i don't fully understand about it: what is the JK-FF for? and is it even necessary, couldn't i just implement the behavior of that JK-FF inside the CPLD since the decoding logic is also in there already?...that also makes me pretty sure i don't need the discrete 74ACH109 and can just do this inside the CPLD, i can even use a counter instead of a simple FF and connect it to the control register so the CPU can change by how much the clock gets stretched

V1.3 is all discrete, hence the AC109. Assuming you're using WinCUPL to program your CPLD, the following code produces the same effect as the AC109:

Code:
Name                JK_flop_test;
Partno              none;
Revision            01;
Date                2021/08/13;
Designer            BigDumbDinosaur;
Company             BCS Technology Limited;
Location            None;
Assembly            None;
Device              f1504ispplcc44; /* ATF1504 in PLCC44 */

property    atmel {output_fast           = off  };
property    atmel {pin_keep              = off  };
property    atmel {preassign             = keep };
property    atmel {tdi_pullup            = off  };
property    atmel {tms_pullup            = off  };

/*                          Signal            Type    Function                  */
/*==============================================================================*/
pin   1                   = RESB;          /* input   system reset              */
pin                       = STP;           /* input   initiate wait-state       */
pin                       = WSE;           /* output  clock control             */
pin  43                   = GCLK;          /* input   global clock              */
/*==============================================================================*/

pinnode    = timer;                        /* wait-state timer                  */

/* LOGIC */

timer.AP   = !RESB;                        /* preset flop on reset              */
timer.CK   = GCLK;                         /* flop's clock source               */
timer.J    = !timer;                       /* here we "wire" the flop to act... */
timer.K    = !STP & RESB;                  /* as a 1-shot timer                 */

/* OUTPUT */

WSE        = !timer;                       /* active-low stop-the-clock output  */

In the above, when STP is driven low the timer will start on the next rise of GCLK (global clock). At the same time, WSE will be driven low. This signal would be wired to PRE on U16b in the V1.3 schematic. Hence U16b will "freeze" with Ø1 held low and Ø2 held high, stopping the MPU. On the next rise of GCLK, the timer will have timed out and WSE will be driven high, releasing U16b and restarting Ø1 and Ø2.

I show STP as an input signal to the CPLD, which was to aid simulation. In actuality, STP would be internally generated from the CPLD logic that defines chip selects to hardware needing a wait-state. GCLK would be derived from Q of U16a, same as in the schematic. Since the CPLD acts as the wait-state timer, the only discrete hardware in the clock generator is U16 and the oscillator. I recommend you use a 74ACT74 for U16, due to the CPLD outputting TTL levels, instead of CMOS.

Attached is a screen grab of the simulator's output.

Attachment:
File comment: JK Wait-State Timer in CPLD
jk_wait_state.gif
jk_wait_state.gif [ 153.34 KiB | Viewed 679 times ]

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Proxy
PostPosted: Fri Jul 08, 2022 6:12 pm 
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Thanks BDD! Currently i'm using Verilog though, that's why i mentioned Quartus in a previous reply about the Bank Address latch.
Specifically i'm using the logic simulator "Digital" to build and test the circuit, and then export it to verilog and synthesize it with Quartus... it's quite the sequence but it has worked pretty much flawlessly with my other CPLD based projects so far.
That's also why i didn't have any "code" to share with this project, it would've just been a screenshot of the circuit:
Attachment:
javaw_9VghTK1QAr.png
javaw_9VghTK1QAr.png [ 450.8 KiB | Viewed 666 times ]

I think i'll redo the entire logic in WinCUPL once i got it finalized and the PCBs ordered, just to see if there would be any noticiable latency difference.

and this right here is the current schematic:

the differences being the newly added '245 for the Data Bus demux-ing, the '74 for the Clock Generation, the Barrel Jack + LM340T for power, an onboard LED hooked up to PB6 of the VIA for debugging and such (PB4 is still unused), the Expansion Connector changed a bit... i gave it access to both the VIA_PHI2 clock and the regular (stretchable) PHI2 clock and also added a signal called "WSE_EXT" which allows an external device to insert wait states into the CPU's Clock.

I still have to probably add a few more Bypass Caps, but if there is nothing hugely wrong with this schematic then i can start to do the PCB layout (i looked over it a few times myself and i cannot see anything obvious that could be wrong)


Attachments:
Uk86mLqQYq.png
Uk86mLqQYq.png [ 202 KiB | Viewed 666 times ]
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BigDumbDinosaur
PostPosted: Fri Jul 08, 2022 8:03 pm 
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Proxy wrote:
Thanks BDD! Currently i'm using Verilog though, that's why i mentioned Quartus in a previous reply about the Bank Address latch.
Specifically i'm using the logic simulator "Digital" to build and test the circuit, and then export it to verilog and synthesize it with Quartus... it's quite the sequence but it has worked pretty much flawlessly with my other CPLD based projects so far.
That's also why i didn't have any "code" to share with this project, it would've just been a screenshot of the circuit...

I can hardly read anything in those graphics.

Regarding the CPLD, the behavior of the wait-state code is an analog of the actual hardware. Although my example is in CUPL, you should be able to make the translation to Verilog.

As for programming the ATF150x, Microchip's (nee Atmel) rendition of CUPL is optimized for their CPLDs' proprietary features, especially logic doubling. I'm not sure if you can make use of those features using third-party software.

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Proxy
PostPosted: Fri Jul 08, 2022 8:20 pm 
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BigDumbDinosaur wrote:
I can hardly read anything in those graphics.

yea sorry about that, it's not really cleaned up that well either, it's mostly just tunnels so i can move stuff around without worrying about wires.
but i do have a B&W version of the schematic down below

BigDumbDinosaur wrote:
Regarding the CPLD, the behavior of the wait-state code is an analog of the actual hardware. Although my example is in CUPL, you should be able to make the translation to Verilog.

yes it was fairly straight forward, for enabling the JK-FF it just checks if either ROM, IO, or the External ~WSE signal are active. (this should be easier to view)
Attachment:
javaw_Vy1rX6WWBP.png
javaw_Vy1rX6WWBP.png [ 77.22 KiB | Viewed 652 times ]

BigDumbDinosaur wrote:
As for programming the ATF150x, Microchip's (nee Atmel) rendition of CUPL is optimized for their CPLDs' proprietary features, especially logic doubling. I'm not sure if you can make use of those features using third-party software.

which came first, Atmel's ATF150x series of the MAX7000 Series? they are compatible with eachother so i assume one company just copied the design from the other. if Atmel's came later i can imagine them throwing in exlcusive features to make it more attractive.


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65C816_SBC_bw.pdf [195.22 KiB]
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BigDumbDinosaur
PostPosted: Fri Jul 08, 2022 8:43 pm 
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Proxy wrote:
...but i do have a B&W version of the schematic down below...

Suggestion: make U9 an ACT245.

Quote:
which came first, Atmel's ATF150x series of the MAX7000 Series? they are compatible with eachother so i assume one company just copied the design from the other. if Atmel's came later i can imagine them throwing in exlcusive features to make it more attractive.

I'm not sure which one was first on the market. Some of Atmel's features may have been for enticement purposes, but others, such as cascaded logic and logic doubling, can make it possible to fit designs that won't fit the same-sized MAX7000 family part.

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Proxy
PostPosted: Fri Jul 08, 2022 8:49 pm 
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i thought the T versions were TTL instead of CMOS, would that work fine with the 65816?
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BigDumbDinosaur
PostPosted: Fri Jul 08, 2022 9:22 pm 
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Proxy wrote:
i thought the T versions were TTL instead of CMOS, would that work fine with the 65816?

A 74ACT245 generates CMOS-level outputs, but recognizes TTL levels as valid input. This characteristic allows the ACT245 to act as a level converter when the selected device is one that generates TTL-level outputs, e.g., the SRAM, and the 65C816 is in a read cycle.

BTW, it appears you have a significant design error, which I neglected to mention in my previous post. If the CPLD is going to be in charge of generating the bank bits, it has to be wired directly to the D0-D7 pins of the 816. As you have it right now, the CPLD won't see anything until Ø2 high, at which time the 816 will be in a data cycle.

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kernelthread
PostPosted: Fri Jul 08, 2022 10:24 pm 
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Shouldn't J1 pin 3 be VIA_PHI2 rather than VIA_CLK? I can't find any other reference to VIA_CLK in the schematic, so I assume it's a mistake.
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BigDumbDinosaur
PostPosted: Sat Jul 09, 2022 1:54 am 
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kernelthread wrote:
Shouldn't J1 pin 3 be VIA_PHI2 rather than VIA_CLK? I can't find any other reference to VIA_CLK in the schematic, so I assume it's a mistake.

Okay, I wasn't the only one who just noticed that. VIA_PHI2 should be called GCLK in this circuit, because it is driven from the "global" clock source that also controls the wait-state function in the CPLD.

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Proxy
PostPosted: Sat Jul 09, 2022 5:21 am 
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BigDumbDinosaur wrote:
A 74ACT245 generates CMOS-level outputs, but recognizes TTL levels as valid input. This characteristic allows the ACT245 to act as a level converter when the selected device is one that generates TTL-level outputs, e.g., the SRAM, and the 65C816 is in a read cycle.

ah i see, shouldn't the 74AC74 also be ACT then? since it takes the ~WSE signal from the CPLD?

BigDumbDinosaur wrote:
BTW, it appears you have a significant design error, which I neglected to mention in my previous post. If the CPLD is going to be in charge of generating the bank bits, it has to be wired directly to the D0-D7 pins of the 816. As you have it right now, the CPLD won't see anything until Ø2 high, at which time the 816 will be in a data cycle.

oh frick, i completely overlooked that and removed the direct databus connection to the CPLD after i added the '245.
luckly i have just enough pins on the CPLD left, i just need to reorder some thing so the free pins are closer to the CPU.

BigDumbDinosaur wrote:
kernelthread wrote:
Shouldn't J1 pin 3 be VIA_PHI2 rather than VIA_CLK? I can't find any other reference to VIA_CLK in the schematic, so I assume it's a mistake.

Okay, I wasn't the only one who just noticed that. VIA_PHI2 should be called GCLK in this circuit, because it is driven from the "global" clock source that also controls the wait-state function in the CPLD.

hmm i thought i used the search&replace function of Kicad to rename all of them at the same time. oh well that's easy to fix.

here the updated version:


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65C816_SBC_bw.pdf [197.57 KiB]
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kernelthread
PostPosted: Sat Jul 09, 2022 8:58 am 
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Proxy wrote:
BigDumbDinosaur wrote:
BTW, it appears you have a significant design error, which I neglected to mention in my previous post. If the CPLD is going to be in charge of generating the bank bits, it has to be wired directly to the D0-D7 pins of the 816. As you have it right now, the CPLD won't see anything until Ø2 high, at which time the 816 will be in a data cycle.

oh frick, i completely overlooked that and removed the direct databus connection to the CPLD after i added the '245.
luckly i have just enough pins on the CPLD left, i just need to reorder some thing so the free pins are closer to the CPU.

It would be a good idea to complete the logic design for the CPLD before getting the PCB made. Even if a design fits into the CPLD it may not fit with an arbitrary pin assignment. Also, even if your original design fits with a certain pin assignment, it's possible that a future modification (even a relatively minor one) can make it no longer compatible with that pin assignment - I have been burned by this on a previous project. The usual procedure is to do the logic design, compile it and let the CPLD fitter assign the pins, then design the PCB on that basis, although it often produces a layout which isn't terribly convenient for the PCB.
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Proxy
PostPosted: Sat Jul 09, 2022 9:21 am 
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I found that the fuller the CPLD is harder it is to move pins around, but in this case the entire logic only takes up 37 Macocells (fitter assigned pins), and changing it to the current pinout on the schematic doesn't change the amount of Macrocells it uses.
with all that space in CPLD i'll see what i can fit in there after everything is ordered, assembled, and working.
i tested an 8-bit hardware multiplier and it did fit but dragged Fmax down too much so i'll probably won't include that one.
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kernelthread
PostPosted: Sat Jul 09, 2022 9:42 am 
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The design that caused problems for me had 90 out of 128 macrocells used.
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plasmo
PostPosted: Sat Jul 09, 2022 2:23 pm 
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Was the design in verilog/VHDL? I have found the fitter does a better job with schematic, either because Quartus is more efficient with schematic or because I can visualize fan-in better so to place LCELL at the right place.
Bill
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kernelthread
PostPosted: Sat Jul 09, 2022 7:41 pm 
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plasmo wrote:
Was the design in verilog/VHDL? I have found the fitter does a better job with schematic, either because Quartus is more efficient with schematic or because I can visualize fan-in better so to place LCELL at the right place.
Bill

No - it was an ATF1508 programmed using WinCUPL. I gave up trying to use Quartus with ATF150x devices because:
1. Even though ATF1502 and 1504 seemed to work OK, I observed incorrect conversions from POF to JED for EPM7128 -> ATF1508 conversions. The POF file programmed onto an EPM7128 worked, but the JED file obtained from POF2JED, when programmed onto an ATF1508, didn't work correctly.
2. Quartus doesn't know about ATF150x extended features such as logic doubling which limits the designs it can be used for.
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