Maybe someone can help me out with this - I’ve been working on several 65CXX projects, all running at 5V. I wanted to integrate FPGAs into the projects. Unfortunately, all the ones I would use run at 3.3v. I know I can’t do any soft CPU’s or anything like that. I just want to create some real interfaces to avoid bitbanging with 65C22s.

I got a 5M570ZT100C5N, to start, an Altera MAX V CPLD, and it does 5V. But, what is the difference between programming this, versus programming, say a MAX 10 or Cyclone 10?

How severely limited is this, and was it a bad idea?

Howdy! I think you'll love working with the MAX V, especially once you get over the tooling, which is… well, let's say “rough around the edges” (though nowhere nearly as bad as, say, WinCUPL). The differences between all these CPLDs are pretty complex—they each have different features, number of gates, support for various interfaces like SPI, and so forth. At the end of the day, it all boils down to what you need out of it, as you can imagine.

These devices are all pretty powerful, however. To give you an idea, I built a fairly functional VGA interface out of a MAX II, which has roughly half the number of macrocells as your MAX V. It works like a treat, and I have very little experience with either CPLDs or electronics in general. So, I suspect that you could do a lot with that MAX V!

Voltage levels are, indeed, a pain. I ended up redesigning my SBC to use 3.3V, which turned out to be the easiest solution, but I think you can find some CPLDs that are 5V-compatible, though they are probably getting harder and harder to come by. (Do note that the MAX V needs to be powered by a 1.8V supply, even though it supports 3.3V on its I/O pins).

One final thing to consider is that the MAX V is, technically, obsolete (as is the MAX II that I use). They are still easy to find, well supported by Intel's tooling, and relatively cheap because they aren't used for new designs anymore, however. There are plenty of newer options that are more powerful, but, usually, also more expensive.

There are many folks on the forums that are much more experienced than me and have built some amazing things using CPLDs—I encourage you to browse and learn from them. Cheers!


—Marco

The simplest answer here is: No difference.

You'll likely be using VHDL or Verilog for your design so all the real complexities will be hidden by the (Quartus II / Prime) tool chain.

You can take the VHDL/Verilog file from your MAX V CPLD design and place it in a MAX 10 or Cyclone 10 design, assign appropriate I/O pins, and upon synthesizing, the design should work just fine on the FPGA.

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Most FPGAs (but not all) need an external EEPROM to hold the bitstream, and most FPGAs (I think) take a few milliseconds to load that bitstream at power-on. I think CPLDs behave much more like a conventional chip, that needs no support circuit and takes no time to start working after power-on.

FPGAs will also, usually, be more expensive, but the main thing going for them is that they are (or can be) a great deal bigger on the inside. If you need the resources, you need the capacity.

Of course considerations like supply voltage, pin count, package style, availability, cost and speed will factor in to your decision too.

I just wonder why so few FPGAs can do 5V.

Probably the same reasons as for any other high density logic device:

1. Smaller geometries have lower breakdown voltages
2. Power dissipation. At a given operating frequency, this increases as the square of the supply voltage.

I have to admit, even the ones that do 5V seem to do so using logic level converters, while natively running at 3.3v.

Since W65C02 and W65C816 work at 3.3V, the easiest approach using MAX CPLD is operating everything at 3.3V. MAX5/10 CPLD have so much resources that 6522 and 6551 functions can easily emulate inside. You don't need ROM, either, since MAX has internal flash sufficiently large to boot and copy more software from SD. So basically you just need W65Cxxx, MAX, RAM, and SD card.

FPGA has everything so you can get rid of W65Cxxx and RAM and do everything with FPGA + SD card.

Bill

> FPGA has everything so you can get rid of W65Cxxx and RAM and do everything with FPGA + SD card.

Although that's true, or can be, not everyone wants to create such a design, so it's not the answer it might seem to be. Probably this thread isn't the place to get into those questions of project preferences - we're covered it before, I'm sure.

Exactly right - that’s a different project altogether

Right now, I’m still working with my 65C265s.

You could take a look at the Altera Flex EPF10k which is a 5V-native FPGA. It is not actively produced anymore but there are a number of these on eBay. The EPF10k10 is PLCC-84 which makes it easy to use, it contains 10k gates, 576 logic elements. Not sure how that compares to the 128 macrocells of the ATF1508, I'm guessing 4-5 times more space? Higher capacities come in QFP packages. It needs a configuration EEPROM called the EPC2, which you can find in PLCC-20. The IDE is Quartus 9.0 which is pretty old

I haven't played with mine yet, but we talk about this family and the tooling needed in this thread viewtopic.php?f=10&t=6975

Here is the datasheet https://nl.mouser.com/datasheet/2/612/d ... 299404.pdf

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I thought most if not all modern FPGAs just have the flash built-in and allow you to hook up an external flash if you feel like it. hmm, maybe that's less common than i assumed.
and the power up time of a few milliseconds is not really an issue if your use something like a DS1813, which pulls the System's reset line low for ~150ms anyways.
if you don't have one you can have the FPGA take control of the reset line, and put a pull down resistor on it. so during power up the FPGA's pins are in High-Z mode so the pull down will constantly reset the CPU, after the FPGA is booted up it can then pull the reset line high and allow the CPU to run.

but yea, due to CPLD's directly storing their configuration directly where they need it, they pretty much have no boot-up time at all.

That's why i like the MachXO2 HC series. it comes in hand solderable package (TQFP), has roughly the same amount of IO as an ATF150x CPLD, and costs around the same as well (~10-15 USD), but of course it has a much much larger logic capacity.
downside is just the fact that they run at 3.3V, so you have to design your entire system around that, or only use the FPGA as an IO device (a VGA Card, Blitter, Co-Processor with a >100MHz Custom CPU, DMA Controller, etc) and connect it via level shifters to your System.

a much larger downside is that due to the current chip shortage it's pretty difficult to find any low cost and hobbyist friendly FPGAs from Lattice, Intel, or Xilinx that are still in stock and without inflated prices.
so CPLDs are almost the only options right now.

I usually use Xilinx xc95...xl CPLDs. They need 3.3V supply voltage but inputs are 5V tolerant, which comes in real handy.

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