In support of my arguments over on this thread: http://forum.6502.org/viewtopic.php?f=4&t=6594

I'm going to do a few real-life experiments. This first one is to see the drive capability of a 74LSxx chip in various environments. I'll check it out in a typical situation where it's original designers expected it to live .. driving 6 full TTL loads. The test load is a 7404. Next I'll check out how well we can drive a load more in tune with our projects .. 6 CMOS loads (a 74HC04). The finally I will overload it beyond the worst case specifications (6 full TTL loads + 8.2K resistor) and see how it does.

Here is it driving the 6 full TTL loads. Measured current draw at the high level is 114uA.
We can see, as expected it fully meets and nicely exceeds specifications for both TTL and CMOS environments.


Now let's have a look at it driving the 6 CMOS loads. Measured current at the high level is 0.58uA. This is basically an open circuit form the perspective of the 74LS chip.
The lack of any reasonable load has this ringing a little, but the 74LS output has absolutely no problem exceeding CMOS input specifications. This is basically no-load performance of the chip. I suspect it would have no issue driving 50 worse case CMOS loads, excepting faulty chips.

Now let's over-load the thing. 6 full TTL loads plus a 8K2 resistor. Measured current is 532uA. This would amount to 13 worst case full TTL loads or about 5,000 typical CMOS loads (ignoring capacitance). Most of us would not exceed that (I think).
Even under these conditions it betters typical CMOS requirements and beats the usual worst case (.7Vcc). It certainly far exceeds "worst case" TTL requirements.

Next I'll test some typical RAM, ROM and PLD devices to see if we should wonder too much why they actually work when the out dated spec sheet test conditions say they might, rarely if ever, not work.

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Bill

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What's an additional VIA among friends, anyhow?

Because the rise and fall times were fairly consistent across the 3 loads it did not raise a red flag. I was just looking to see if the VIl and VIh specs were being met for the different environments. I will measure the scope lead capacitance and the rise/fall times.

Okay, got the timing and cable measurements:

6 CMOS loads - rise = 39ns, fall = 24ns

6 TTL loads - rise = 41ns, fall = 26ns

Overload - rise = 36.5 ns, fall =27.5ns

Scope probe and lead (attached to scope) measures 17pF

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Bill

I know TI published logic family's typical characteristic in their data book. I looked up chapter 1 of my TTL,LS,S databook and see many detailed charts of output characteristics vs temperature and load. Voh of 3.4V at room temperature, no load is typical. I know there are similar typical characteristic graphs for TI's HC, HCT, AC ACT family. I know I had these books but they are probably moth-eaten in back of my garage!
Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

This sounds very low in my experience. The TI sheet I have for their 74LSXX quotes 3.4V @ 400uA for the typical value. My guess is that their is a fudge (CYA) factor in there as I'm getting 3.6V @ a 25% overload. Exact same result for 3 different chips.

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Bill

Agreed. I think, however, we will see much improved rise and fall times from the CMOS devices in the next stage of the test.

This one was entirely focused on loading. 74LSXX would not be expected to perform well at very high frequencies. However, they should perform well enough at frequencies under about 8MHz. All that said, I would not use TTL at all these days at anything above 2MHz.

BTW, does anyone know why slew rates are not a part of the spec sheets for these TTL parts?

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Bill

Very informative. Thanks for posting!

That little dip in the middle of the positive edge on all three traces ... that's not ringing is it? It looks to me like it's in a very bad place if we're worried about glitches, but I'll defer to the more experienced folks to confirm or deny this.

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I think it's a bypassing/inductance issue. This was just a first pass at all this and was quickly thrown together on a solderless breadboard. I'll do a little sleuthing to figure it out and see if I can clean up things before I move ahead.

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Bill

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I might guess it's ground bounce (very much related) - worth mentioning, I think, because every chip, and the scope probe, will reference a signal level to their local ground. The scope probe, particularly, needs to be seeing something very like the same ground as the chip that's receiving the signal:

I re-built the initial test circuit on a PCB keeping the connections as short as possible and there has been improvement. The power rails are .1" wide traces of 1oz copper and bypass capacitors have been placed between the power pins of each IC and between the ICs.

The total capacitance of the 6 CMOS inputs measured in circuit is 4.6pF (Edit: This was a measurement error. The actual value is 36.4 pF of which 11.6 is contributed by the circuit). Add to that the scope/probe capacitance which measures 16pF without the clip.

Rise and fall times have improved dramatically. Rise (to 3.5V)is now 15ns and fall is 5ns.

Now, using a whisker ground on the probe most of the ringing is gone, especially on the falling edge. However, the dip in the middle of the rising edge is still there. It's far less, but still there. It also reduces as the load increases. Both 74xx and 74lsxx produce that dip. 74ACxx does not.

Is it a measurement artifact?

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Bill

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Yes, that's the total of all 6 CMOS inputs as a group.

I should pull the chip to see how much of that is the circuit.

Edit: Made an little error. Yeah, that 4.6 pF was just a single input. All 6 in circuit measure 36.4 pF of which 11.6 is contributed by the circuit. So the 6 inputs total 24.8 pF (or an average of 4.1) which is more in-line with specs.



I guess it could be. That would be a red flag against using TTL to drive CMOS.

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Bill