Hello everyone!

Following in the footsteps on this previous topic:

viewtopic.php?t=2883

In an effort to maximize compatibility between these two processors, I have been analyzing their pinout differences. The idea is that I want to be able to have drop-in replacement support for either processor. That is, if using a 65C02, it would 'act' as if it were in the 65C816's Emulation mode permanently. I have put together a pinout comparison between the W65C02 vs. W65C816, using the WDC datasheets. The previous topic was using the original 6502 pinout as a guide.

The biggest offenders are:
Pin 3 - PHI1O (output) on 65C02, but ABORT (input) on 65C816
Pin 7 - SYNC (output) on 65C02, but VPA (output) on 65C816
Pin 38 - SOB (input) on 65C02, but MX (output) on 65C816
Pin 39 - PHI2O (output) on 65C02, but VDA (output) on 65C816

Thankfully Pin 3, 38, and 39 on the 65C02 are rarely used, so leaving Pin 39 unconnected and putting 3.3K pull-up resistors on Pins 3 and 38 will work.

I have seen Pin 7 used in Jeff's "illegal instruction" technique (here: viewtopic.php?f=4&t=1945), and perhaps in other places, but those illegal instructions are no longer illegal on the 65C816. Thus, for maximum compatibility, the SYNC pin should go unused on the 65C02, and simply leave this unconnected.

Pin 35 is a NC on the 65C02, but is the E (emulation) pin on the 65C816. Putting at 3.3K pull-up resistor on this will tell a 65C816 circuit with a 65C02 drop-in replacement that it is simply in 'emulation' mode. BUT, the 65C02 datasheet says to leave it not connected. For safety reasons, leave unconnected and have the circuit operate under either condition.

For the banking/data pins, following the advised circuit setup from the 65C816 datasheet is recommended (after all). If the timing is right, you *could* replace the '573 with a '273.

Other than that, all other pins seems identical!

Did I get it right? I am willing to alter, edit, change, or delete whatever necessary so as not to confuse future viewers.

Thanks everyone!

Chad

EDIT: Added an example circuit, THEN I deleted it! I also altered the image below, twice.

Chad, the '273 idea is clever but IMO it seems unnecessary. While in Emulation Mode the '816 will generally keep the Bank Address equal to zero anyway. (Non-zero bank addresses can be produced while in Emulation Mode but only in certain limited circumstances -- for example, in response to a Long fetch or store. I don't recall the exact details offhand. But in any case, the user can easily choose to avoid non-zero banks by simply avoiding using the new opcodes.) (Or not!)

Here's my own pinout cheat sheet, BTW. The red dots are just a visual aid, drawing attention to places where a pin definition differs.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I guess I think like a mathematician sometimes, trying to account for every single situation possible. It would be highly unlikely for an '816 user to do something silly with/in Emulation mode, but JUST IN CASE, with the '273 they will be forced back into Bank 0 whither they like it or not Tomato tomato. Thank you Jeff, I really like your pinout diagram!

Chad

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

(Just for reference and for completeness: a couple of Acorn's designs use SYNC - we saw a failed board where that particular 6502 was fine, other than the SYNC pin. But I agree it's relatively rare to use it in a system. Hoglet's trace decoder does not require, but recommends, SYNC be connected. Then again, none of the above have an '816 angle.)

Thank you BDD.



But:


(emphasis added)

???

I admit I don't know everything, but when it says that it is not connected internally, then, what harm can possibly be done? I am willing to listen.



Let's do a hypothetical. Say we reset and we are in Emulation mode, Bank 0. I then go to Native mode, play around with Bank 1 or something. Then I suddenly want Emulation mode again, but in Bank 1. If I am understanding correctly, I would then re-enter Emulation mode, but be 'stuck' in Bank 1, lest I call those absolute long addressing modes. With the '273, I would be forced back automatically to Bank 0 regardless of where I was beforehand. Am I understanding this correctly?



I'm seeing from the W65C02 datasheet that SYNC is an output-only pin. Yes? Or are you saying it is recommended to use it in general 65XX circuits? I myself have never used it thus far, but I have never done anything particularly fancy either.

Thank you both!

Chad

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I came to about the same conclusions when I looked into the changes needed to use a 65816 in my 65C02 builds several months ago. I got all of my 65C02 builds running with a 65816 with just the pin 3 and 38 changes.


Interestingly, when I first looking into building a 65816 system, I considered using a '273 because I didn't have a '573 on hand. But for some reason I got focused on the "transparent" nature of the '573 and just waited for my Mouser order to arrive instead of trying the '273.

I guess this highlights a possible design difference from using the '273 as a '573 replacement. The '573 will pass through the new bank byte beginning at the latest 33 ns after the falling edge of Ø2. The '273 will not update the bank byte until sometime later, on the rising edge of Ø2. I suppose this could mean that faster memory is needed in a '273 system than would otherwise work in one with a '573. I haven't done any timing diagrams, but I'm guessing the difference isn't material in most common use cases.

> I'm seeing from the W65C02 datasheet that SYNC is an output-only pin. Yes? Or are you saying it is recommended to use it in general 65XX circuits? I myself have never used it thus far, but I have never done anything particularly fancy either.

Indeed, SYNC is an output, and is rarely used.

You're right. And it's not a trivial difference, given that that the /WE pulse sent to RAM usually begins on the rising edge of Ø2.

The Bank Address will appear on the outputs of a '573 early enough that it can be decoded and the appropriate memory chip enabled before the /WE pulse begins. But the 273's delayed delivery of the Bank Address means no timing margin for decoding; hence there's a high risk of rogue writes to unintended addresses.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Now, THAT makes sense. I did go to the datasheet, and you are exactly right, the '273 could/would make unintended writes to very fast RAM. I was mistaken on it's use here because I technically hit the clock to earlier on my own designs. PHI2 is obviously not good enough. Thank you, both, for recognizing that.

I deleted that schematic, as it was incorrect in some circumstances. I edited the first post a bit as well.

So, I would still like to know about the E pin. Is it safer to leave it unconnected, perhaps use a jumper? Sure. But I still don't know if "internally not connected" could actually have an effect. Any advice there is much appreciated.

Thank you again! Good catch.

Chad

It may seem natural to think of Native Mode as being something that turns on many extra capabilities. But I think better insights are revealed if we switch things around and think of Emulation Mode as something that turns off certain capabilities.

When the '816 was created, the designers had their hands full, giving Native Mode its extensive sophistication. Then the last step of the design process was deciding how to inhibit certain features in order to implement Emulation Mode. And it would be senseless of them to waste any extra effort. Their goal was to do the minimum possible in order to ensure that 6502 code can run with no surprises in Emulation Mode.

Certain measures could not be avoided. For example, it was necessary to take deliberate steps to ensure that A, X and Y always remain 8-bit, regardless of any value that might get loaded into the P register.

But one thing the designer's didn't have to bother with is the new opcodes introduced on the '816. '816 opcodes don't appear in 6502 code, so it would be wasted effort to take deliberate measures to prevent their execution. So, no deliberate measures were taken, and many of the new opcodes execute with complete success! Others suffer partial or complete failure, but these are generally just incidental effects rather than a deliberate effort. For example, MVP and MVN end up being badly crippled simply because X and Y are restricted to 8 bits.

Published documentation doesn't always make it clear how the new opcodes will behave in Emulation Mode, but I think it's fairly safe to use the following assumption: barring inescapable factors (for example, the issue noted re MVP and MVN), all the new opcodes will work.

For example, BDD mentioned the absolute long addressing modes, but I believe the Direct Indirect Long modes will work as well. (And all these modes can cause the Bank Address to briefly deviate from zero.)

And I think even Long control transfers will execute successfully, causing the Bank Address to become non-zero for extended periods until you JML or RTL back to bank zero. I wasn't able to verify this. But the Eyes and Lichty manual describes PBR as being initialized to zero at power on. I don't see any reason why it would need to held at zero continuously, so I expect the designers took a laissez faire approach and merely caused PBR to begin at zero.

I hope these remarks are helpful. Chad needn't be concerned about getting stuck in a non-zero bank. He can jump out of that bank just as easily as he jumped in.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I can confirm that I've run code in Bank 01 while in emulation mode. For simplicity, I disabled interrupts.

Just as well. A deliberate effort was made to ensure that, in Emulation Mode, the address pushed to stack is only 16 bit, not 24. Hence it'd be impossible to successfully return after the ISR completes.

So, it's possible to execute code in non-zero banks, and yet it's infeasible to have interrupts enabled when you do. Like the situation I mentioned regarding MVP and MVN, it's another quirky outcome of their minimal-effort approach. Their only priority was ensuring that 6502 code runs with no surprises.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

(I think you could run interruptible code: your code would need to leave a public record of which bank it's in, and the ISR would need to contrive a long return. Acorn's systems already do something a little like this with "sideways" RAM banks.)