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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Ok so I also need to redo my decoding logic, a multiplexer that uses the CPU data bus while PHI2 is low and the bank register while it's high should in theory replicate the behavior of a transparent latch.

SYS_CLK is the "system clock" outputted by the CPLD to the CPU, VIA, and expansion port.
it is internally selected from 2 separate external clock sources (the FTDI chip and the onboard oscillator)

IRQ_CPU is the combined interrupt signal from the VIA, expansion port, and interal interrupt source that goes from the CPLD to the CPU.

And there was some small misunderstanding/miswording. I don't plan on using RDY in this system, you can see the pin just being pulled high in the schematic.
I know how much of a pain RDY is to use with the 65816.
What I meant to say there was "the RDY signal worked fine on my 65c02 so I assume that the control signals I have on this SBC (SYS_CLK, IRQ_CPU) should be fine too"

And lastly, i agree that USB on its own likely won't be enough when I start throwing expansion cards at it, ultimately I just wanted to avoid the need for multiple cables to get it running.
But I guess I'll just have to swallow my pride and only use USB for data and a barrel jack + regular for power due to the future potential power draw. I hope the 800mA regulator I choose is good enough, I'm open for recommendations of better/cheaper ones though!
The FT240X datasheet has an example circuit for an externally powered configuration. I assume that should work fine.

And speaking of barrel jacks, there are a billion different types and sizes, which one would be the most common and recommended one for hobbyist stuff?

Regarding logic threshold issues with CPLDs driving 65816 pins, this project had a CPLD driving the data bus of a 65816:

viewtopic.php?f=4&t=6695
https://www.retrobrewcomputers.org/doku ... o:ovrclk65 (schematic is here)

and that seemed to work up to 30+ MHz.
I guess it's one of those things which will quite likely work, but isn't 100% guaranteed. According to the ATF1508 data sheet (graph on page 17) the output voltage is around 4V for very low current drain from the output; it's around 3.2V for 10mA drain. I seem to remember a post on here somewhere where somebody measured the logic threshold of a 65816 by making use of instructions which differ in one bit of the opcode. The logic threshold was measured at around 2.65V (just over 50% VDD). The 'gain' is very high - i.e. the voltage only needs to be a very small amount above or below the threshold for it to be recognized consistently. I'm not sure how variable that threshold is likely to be over temperature and over reasonable VDD variations, but it seems quite likely that 3.2V would be OK, although there would be reduced noise immunity.

so since there is nothing else on the bus between the CPU and CPLD the current draw should be rather small (atleast i would assume so), therefore the CPLD's output voltage should be high enough for the CMOS chips to recognize properly.
that would explain why the RDY signal on my 65c02 SBC works flawlessly despite the voltage drops, it was just a direct connection from CPLD to CPU.

but utlimately I think the 74AHCT245 would be the better option, it frees up some pins on the CPLD and could maybe be faster than the current plan (would it be faster? the CPLD has to generate the OE and DIR signals for the '245 so the final delay would be the '245's output latency plus the CPLD's pin-to-pin latency instead of only being the CPLD's pin-to-pin latency)
the only real downside is that it takes up space on the PCB. but i'll throw away the entire PCB layout anyways and redo it from scratch once i actually have the whole circuit figured out.

but that still leaves the question of the other TTL to CMOS connections:

• IRQ_CPU: CPLD -> CPU
• CS_VIA: CPLD -> VIA
• SYS_CLK: CPLD -> CPU/VIA/Expansion

But I did find this site: http://www.interfacebus.com/Design_Translation.html that shows a pull-up being used to ensure that the TTL output voltage is high enough for a CMOS chip.
can i just use the same technique here? using a 3.3k or 4.7k resistor array to 5V. it would definitely be a better option than adding another 74xx Logic IC.

Out of the overclock experience is an updated CRC65 that can accommodate both W65C02 and W65C816. It is a simple design where CPLD, RAM, compact flash and external bus connect directly to W65C02 or W65C816. The nominal operating frequency is 14.7MHz. Both Altera CPLD datasheet as well as Atmel ATF150x datasheet has a graph showing the CPLD output stage can drive to about 3.8V, so certainly not an issue with W65C02 but maybe an issue (on paper) with W65C816 since its Vih threshold is 80% VCC. I don't have equivalent graph for RAM output drive nor CF output drive characteristics, but these are CMOS devices capable of driving high output to 3.5V or more.

My other experience with W65C816 is a CPLD-based Apple II+ accelerator, UltraWarp 2. A dozen boards were produced and tested by myself and shipped to a small group of Apple II enthusiasts. Like CRC65, it is also a very simple design with W65C816 directly connected to CPLD and RAM. The production yield was 11 out 12. The CPLD of the 12th board was replaced and then it worked. The nominal operating frequency is 14.7MHz but feedback from users showed stable operations at 20MHz.

Bottom line is W65C816's 0.8Vcc high threshold is overly pessimistic.
Bill

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

well did I mentioned in the first post that i wanted to use 2 clock sources. the primary one being the FTDI chip, which supplies a 24MHz signal (min output voltage of 2.97V). and a secondary clock from the expansion port. that way i would avoid the need for an onboard Oscillator but still have the option to switch one if an Expansion card includes one for the CPU.
but dealing with switching independent clock sources with discrete logic is a pain, so i'll also have to throw that away too and just settle for a single onboard Oscillator.

I feel like i'm slowly giving up every feature i had planned, it's dragging my mood down a bit.

i'll respond to the rest tomorrow, it's 23:00 and i have work in like 7 hours.

Yes; in this thread: TTL Compatible... NOT! ( modern WDC CPU's )

Yes, exactly. 3.2V would be kinda-sorta OK, although there would be reduced noise immunity. (If the CPU truly were TTL compatible then its logic threshold would be around 1.5V instead -- a better match, if TTL levels must be accommodated.)

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

alright i got some sleep!


yes the CPLD uses an interal 8 bit register to latch the Bank Address, in which case would there be any benefit of generating PHI1 in the first place?
because then i could use Dr Jefyll's single IC Clock Strteching circuit to generate PHI2 (and PHI2_VIA): viewtopic.php?f=4&t=5504
and just pass that to the CPLD to be used for the Bank Latching (and generating the OE_MEM and WE_MEM signals).
the P0-3 inputs could be directly wired to the CPLDas well, so i can control the amount of stretching done depending on what device/address is accessed, or even have the CPU control it through the interal control register, (or just hardwire a value in the CPLD).

the original reason i wanted to have a selectable clock is because i knew using RDY on the 65816 was annoying, so i just wanted to throw that workload onto the CPU to deal with manually. but with a clock stretching circuit i no longer need multiple clock speeds.


So my current circuit would likely work perfectly fine. But I've already committed to the '245 due to the speed and fewer CPLD pins used.

Yea I think the simplest option is to just make USB data only, and use the Barrel Jack as the only power source, like I mentioned in a previous post the FT240X's datasheet has an example circuit for an externally powered configuration where it can even recognize if a USB cable is plugged in (by checking the USB Vcc pin). So I'll just be using that.
Also I cannot find any specific dimensions when searching for "DC-10" online. So I think I will just choose the 2.1mm DC jack standard, it seems to be the most common so finding wall adapters for it should be easy.

Yea it's clear that when it comes to regulators kind of out of my element, I didn't even think they would need heat sinks because I doubt they would've drawn that much current.
The LM340T5.0 seems like a popular choice so I'll also go with that. When it comes to PCB placement I'll see if I can place it somewhere on the edge so I can screw a heatsink onto its back without interfering with another component.

I hope it's a follow/hold transparent register (that works like a '573), not an edge-triggered register (that works like a '574). Is this an issue that's on your radar? Programmable Logic Devices and their design tools tend to steer you toward edge-triggered registers. But a transparent latch is preferable as it'll make the Bank Address bits available sooner.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Yes i have thought of that (or atleast tried to), my idea was to use a regular 8-bit D-FF with a Multiplexer at the output that switches from the Databus to the contents of the FF when PHI2 goes high, and back when it goes low again.

the only thing i'm not sure about is the small window of time when the MUX flips over, because i don't know what it would output during that.
alternatively i also made an actual D-Latch, and Quartus seems to just accept it (it even recognizes it as a Latch and just spits out a warning). here's the RTL View of 1 bit of the D-Latch:

In Quartus there is a "latch" primitive. During compilation it will warn you that timing analysis does not support analysis of latch. I used "latch" for bank register of 65816 for the exact reason that has been very well explained in this thread.
Bill

That FF with multiplexer look like recipe for disaster to me due to potential glitches when phi2 changes.
Just what happens if the multiplexer is faster switching than the FF propagating the new address.

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

alright i've opted to just use BDD's Clock circuit from his POC v1.3 instead of Dr Jefyll's circuit.
despite BDD saying it i still somehow forgot that the '245 needs PHI1 to work and i didn't want to bother routing that through the CPLD.
here a link to the datasheet of his POC 1.3 that contains the circuit on page 5: download/file.php?id=11876
but one thing i don't fully understand about it: what is the JK-FF for? and is it even necessary, couldn't i just implement the behavior of that JK-FF inside the CPLD since the decoding logic is also in there already?
EDIT: Ignore that last part (i wish this site supported strikethrough text with [s][/s]), i figured it out. the JK-FF is there to limit the amount of wait states inserted, without it the ~WSE signal would never be pulled high again because the CPU would never reach the next falling edge, effectively Halting it. but with the JK-FF it would only react to the falling edge of the ~WSE signal, inserting a single wait state and then lets the clock continue like normal.
that also makes me pretty sure i don't need the discrete 74ACH109 and can just do this inside the CPLD, i can even use a counter instead of a simple FF and connect it to the control register so the CPU can change by how much the clock gets stretched